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SECTION
4
DIAGRAMS
RF PLL Free-run Frequency Check
[MAIN BOARD]
441
BLOCK DIAGRAM
Procedure :
- Component side -
1. Connect frequency counter to test point (PLCK) with
lead wire.
Wakes
frequency counter
aie
MHz.
Lay
PRSSSG0K
aN
OPTICAL PICK-UP BLOCK
Lacko@)
@un:
DETECTOR
iesoi
:
7
3
onaivat tena
saver | 20302
Adjustment Location :
PROCESSOR
FILTER SCLko
ect
x
*
0
D4BAS
LAY
Ainyo
— MeLKG
D)
H
A
r
}
PROCESSOR:
XLT
'
any
[BD BOARD)
i
e
ais
d
.
@,
i
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oaTa
Bess
.
i
SR
|
hag
é
- Solder side -
i
xTAL@
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5
aL
0
if
EY
rox G9
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ov
AS
APPROX
400mVp-p
a
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PLAY
@
i
EOE
secs ey. 8
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ry
FE
10404
TE ORFO
system ConTROL
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VC
°
On
PLCK
$
wore +
1¢301
stot
Sherr
SETH
———
av
Sadar
SPINDLE
272
s274
8423-425.
NoTOR
(oso
oko
FLo4ot
$427. 428 431,
1c102
BRIVE
DRIVE
sutton sitton | Fuuonescent | | 8438-442
ADJ
sPINDLE/SLEq
TNOZGATOA
MOTOR ORIVE
TUBE
eure Fon
if
OX
ow
sured'
ines
®
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LoaptNé 'woroR
sioe
wios
sueD woTOR
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