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EN 48
7.
QFU2.1E LA
7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 General Power Architecture
7.4 Back-End Processing
Notes:
•
Only new circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring-, block- (see chapter
9. Block
Diagrams) and circuit diagrams (see chapter
Hybrid
Tuner
DVB
DVB-S2
DVB
Tuner
2013-Apr-05
Circuit Descriptions
T2
S2
HDMI
9385
Figure 7-1 Architecture of FUSION platform 2012
10. Circuit Diagrams and PWB
necessary, you will find a separate drawing for clarification.
7.1
Introduction
The QFU2.1E LA chassis is part of the FUSION platform and
covers sets in the 6xxx range.
7.1.1
FUSION 2011 Architecture Overview
For details about the chassis block diagrams refer to
Block
Diagrams. An overview of the FUSION 2012 architecture
can be found in
DDR 1 GB
4 × 2 Gb
64/48
DVB-T/C
ISDB-T
Analogue
Fusion
Analogue
CI+
ETH
PHY
back to
div. table
Layouts). Where
Figure
7-1.
MLC
FLASH
FLASH
1 GB
2 GB
PQ
USB
HUB
CLASS-D
BL
FPGA
19280_098_120503.eps
chapter 9.
AUDIO
AL
BL
120503
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