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Circuit Diagrams and PWB Layouts
SSB: SPDIF/Debug/RS232 Int.
1
1
2
2
A
A
1J10 D2
1JEB D5
1JEE D8
1JEH C9
1J11 D1
1JEC D6
1JEF D9
2J11 D1
1JEA D4
1JED D7
1JEG D9
2J12 D2
B
B
1
C
C
A
D
D
B
E
E
SPDIF-OUT
F
F
C
G
G
RXD_PC
TXD_PC
D
H
H
UART
SERVICE
CONNECTOR
FJ13
1
I
I
J
J
MULTI 12NC : 3139_283_30162
BD 12NC
: 3139_283_30172
1
1
2
2
PB52.3HU LA
10.
3
3
4
4
5
5
2J61 B3
2JE2 B5
2JE5 B5
3J50 A2
3JE0 D5
3JE3 C8
7J50 B2
2J62 B2
2JE3 B7
3J11 D3
3J51 B3
3JE1 C5
6J11 D3
7JE2 A6
2JE1 A7
2JE4 B7
3J12 D3
3J53 B3
3JE2 B8
6J12 C3
FJ11 D2
2
3
4
+3V3
SPDIF
IJ54
IJ53
2J62
100n
7J50
74HCT1G08GW
1
IJ58
2J61
IJ56
3J51
4
IJ57
SPI-OUT
2
220R
100n
RXD
TXD
6J12
RXD0
BAV99 COL
2
1
+3V3-STANDBY
TXD0
3
FJ12
IJ12
100R
3J12
FJ11
100R
3J11
3
2
1
+3V3-STANDBY
6J11
BAV99 COL
2
3
4
3
3
4
4
5
5
EN 72
6
6
8
8
7
7
FJ12 D2
IJ12 D4
IJ56 B3
IJE1 B6
IJE4 B7
IJE7 B6
IJEA B7
FJ13 D1
IJ53 B2
IJ57 B3
IJE2 B7
IJE5 B6
IJE8 B7
IJEB C6
FJEC A6
IJ54 A2
IJ58 B2
IJE3 B6
IJE6 B6
IJE9 B6
IJEC C7
5
6
DEBUG / RS232 INTERFACE
+3V3-STANDBY
FJEC
7JE2
ST3232C
16
Φ
VCC
RS232
2JE2
IJE1
1
C1+
100n
V-
IJE3
3
C1-
2JE5
V+
IJE5
4
C2+
100n
IJE6
5
C2-
IJE7
1
1
T1
T1
IJE9
1
0
IN
OUT
T2
T2
IJEB
1
3
R1
R1
IJED
8
IN
OUT
R2
R2
15
IJEF
3JE1
100R
3JE0
100R
1JEA
1JEB
1JEC
REF EMC HOLE
REF EMC HOLE
REF EMC HOLE
5
6
CHN
DC398881
SETNAME
CLASS_NO
3PC333
BDS MODULES
-- -- --
1
PCB SB PB522_LN
2009-05-15
2
2009-07-31
3
NAME
YiPing Guo
SV
CHECK
7
7
6
6
8
8
2009-Oct-09
9
9
10
10
11
11
12
12
IJED C6
IJEE C7
IJEF C5
7
8
9
2JE1
100n
6
IJE2
2JE3
100n
2
IJE4
2JE4
100n
3JE2
1
4
IJE8
RSRX
7
IJEA
100R
3JE3
1
2
IJEC
RSTX
9
IJEE
100R
1JEH
REF EMC HOLE
1JED
1JEE
1JEF
REF EMC HOLE
REF EMC HOLE
REF EMC HOLE
REF EMC HOLE
7
8
9
3139 283 3017
SUPERS.
43
10
130
DATE
2009-05-15
ROYAL PHILIPS ELECTRONICS N.V. 2009
C
9
9
10
10
1
11
1
12
12
13
13
A
A
B
B
C
C
A
D
D
B
E
E
F
F
C
G
G
1JEG
D
H
H
I
I
2
2009-07-31
2
2009-07-28
JJ
16
A3
13
13
18730_515_090918.eps
090918
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