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3.13.9
Floating-Point Processor
3.13.9.1 General
The MPC533 implements all floating-point features as defined in the UISA, including the
non-IEEE working mode. Some features require software assistance. For more information
refer to the RCPU Reference Manual (Floating-point Load Instructions) for more
information.
3.13.9.2 Optional instructions
The only optional instruction implemented by MPC533 hardware is store floating-point as
integer word indexed (stfiwx). An attempt to execute any other optional instruction causes
an implementation dependent software emulation exception.
3.13.10 Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point MPC500
load/store instructions in the hardware.
3.13.10.1 Fixed-Point Load With Update and Store With Update
Instructions
For load with update and store with update instructions, when RA = 0, the EA is written
into R0. For load with update instructions, when RA = RT, RA is boundedly undefined.
3.13.10.2 Fixed-Point Load and Store Multiple Instructions
For these types of instructions, EA must be a multiple of four. If it is not, the system
alignment error handler is invoked. For a lmw instruction (if RA is in the range of registers
to be loaded), the instruction completes normally. RA is then loaded from the memory
location as follows:
RA ← MEM(EA+(RA-RT)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions
Load string instructions behave the same as load multiple instructions, with respect to
invalid format in which RA is in the range of registers to be loaded. When RA is in range,
it is updated from memory.
3.13.10.4 Storage Synchronization Instructions
For these type of instructions, EA must be a multiple of four. If it is not, the system
alignment error handler is invoked.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 3. Central Processing Unit
User Instruction Set Architecture (UISA)
3-45
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