Table of Contents
Advertisement
ECTION
D Block basically constructed to operate with-
it adjustment.
Therefore,
check
each
item in
'der given.
se YEDS-18 disc (3-702-101-01) unless otherwise
dicated.
se the oscilloscope
with
more
than
10M2
im-
sdance.
lean an object lens by an applicator with neutral
stergent
when
the
signal
level
is low
than
ecified value with the following checks.
ve Check
oscilloscope
BD
board
>
1O
TP (FEI)
oO —0F
TP (VC)
O~—w-—=0 -
dure :
nnect
oscilloscope
to test
point
TP
(FEI) on
| board.
nnect between test point TP (FE) and TP (VC)
lead wire.
med
Power
switch
on and actuate
the focus
ch.
(acutuate the focus serch when disc table
moving
in and out.)
ack
the
oscilloscope
wavefrom
(S
curve)
is
nmetrical
between
A and B. And
confirm
peak
peak level within 3+ 1Vp-p.
ye waveform
symmetry
within
3£1Vp-p
ter check, remove
the lead wire connected
in
p 2.
* Try
to mesure
several
times
to make
sure
that the ratio of
A: B or B: A is more than
10: 7.
* Take sweep time as long as possible and light
up the brightness to obtain best waveform.
RF Level Check
oscilloscope
BD
board
>
IO
TP (RF) O~—,0F
TP (VC) Om-—0 -
Procedure :
1.
Connect
oscilloscope to test point TP
(RF) on
BD board.
2.
Turn Power switch on.
Put disc (YEDS-18) in and playback.
Confirm that oscilloscope waveform
is clear and
check RF signal level is correct or not.
Note:
Clear RF signal waveform means that the shape "©"
can be clearly distinguished at the center of the wave-
form.
VOLT/DIV
; 200mV
RF signal waveform
TIME/DIV - 500nS
WA
LO
17,
YY
E-F Balance Check
oscilloscope
BD
board
a ee | ©
TP (TEI)
O—t-—o}
TP (VC)
ow—lo-
Procedure:
1. Connect
test point TP (ADJ) to ground
and
TP
(TEO) to TP (VC) with lead wire.
2. Connect
oscilloscope
to test
point
TP (TEI) on
BD board.
3. Turn Power switch on.
4.
Put disc (YEDS-18)
in and playback.
5.
Confirm
that
the oscilloscope
waveform
is sym-
metrical on the top and bottom in relation to OV,
and check this level.
Traverse oscilloscope
symmetry
level: 2+1Vp-p
6.
Remove the lead wire connected in step 1.
RF PLL Free-run Frequency Chect
Procedure :
1. Connect
frequency
counter
to tes! point (PCLK)
with lead wire.
fi
ncy count
Main board
sb
ba
—
TP (PCLK) O~t—0#
3.
Confirm that reading on frequency counter is
4. 3218MHz.
2.
Turn Power switch on.
Focus/Tracking Gain
This gain has a margin, so even if if is slightly off.
There is no problem.
Therefore, do not perform, this adjustnent.
Please note that it should be fixed to nechanical cen-
ter position when you
moved and do sot know
original position.
Adjustment Locations:
{BD board}
— 33
SECTION 6
6-1. SEMICONDUCTOR LEAD LAYOUTS
CXA1372AQ
(TOP VIEW)
CXD2500AQ
32
GP1US9XB
+ Vout
2 Vee
3 GND
LA6525M
{TOP VIEW)
M5218AFP
PST572E
DIAGRAMS
STK- 4132MK2
2803112
ca
in
MARKING
SIDE
VIEW
2SK246- GR3
TA7272P
2 gh ig.
12345678910
MARKING
SIDE
VIEW
DTZ3.9B
18$352
1S$355
DTA114ES
DTA144ES
DTC114ES
/
DTC143TS
ci
2SB1094- LK
CATHODE:
2SC2603-EF
28C2724-CD
2SC3622A- LK
EC10DS2
2SD2012
| |
Cathode
|
oo
HZS6A1L
UZL- 9M2
11ES2
DTA124ES
oe
DTC144ES
2SA1175-HFE
LETTER
SIOE
Anode
NJL5165K-B
—34—
Advertisement
Table of Contents
