Asus AAEON GENE-APL7 User Manual page 35

Pin Pin Name
14 LVDS_DA2+
15 LVDS_DA3-
16 LVDS_DA3+
17 DDC_DATA
18 DDC_CLK
19 LVDS_DB0-
20 LVDS_DB0+
21 LVDS_DB1-
22 LVDS_DB1+
23 LVDS_DB2-
24 LVDS_DB2+
25 LVDS_DB3-
26 LVDS_DB3+
27 LCD_PWR
28 GND
29 LVDS_B_CLK-
30 LVDS_B_CLK+
Note: LCD_PWR can be set to +3.3V or +5V by configuring JP2 and JP5 for dedicated
port. Driving current supports up to 2A.
Chapter 2 – Hardware Information
Signal Type
DIFF
DIFF
DIFF
I/O
I/O
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
DIFF
PWR
GND
DIFF
DIFF
Signal Level
+3.3V
+3.3V
+3.3V/+5V
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