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VSR-2000
Recording System
The video and audio signals from the BKSR-2020/2021
(encoder) are compressed and recorded on SDRAM of a
PCI control circuit as MPEG data.
The PCI control circuit on the PU-113 board transfers the
SDRAM data on each encoder board to the PU-113 board
according to the instructions from the system control block
of the VSR-2000 and records it on the HDD array.
Playback System
On the PU-113 board, the data is read from the HDD array
according to the instructions from the system control
block, and transferred to SDRAM on each decoder board.
On the BKMA-2030/2031 (decoder), the compression data
transferred to the SDRAM are expanded, decoded to video
and audio signals, and then output.
HDD Array Block
During recording, on the PU-113 board, the compression
data sent via a PCI bus is distributed into four HDDs and
then recorded. Simultaneously with recording, parity data
is generated from the original data and recorded on the
parity HDD.
During playback, the data read from four HDDs is sent
through a PCI bus to the decoder.
If one HDD can normally read no data due to failure, the
data of the defective HDD is recovered based on the data
of the parity HDD and remaining three HDDs.
VSR-2000
Section 6
Circuit Descriptions
SY-283 (with CCM-37A)
The disk protocol control signal from a host controller is
input from the REMOTE terminal and sent to the DPC
(disk protocol controller) CPU (IC513) on the SY-283
board. The DPC CPU interprets the received control
command and issues the internal command to the MAIN
CPU (IC306) via the dual port RAM (IC501, IC529). In
the case of status request, the status information of the
MAIN CPU is read through dual port RAM and is sent to
the host controller.
The FSE (file system engine) CPU (IC410) on the SY-283
board manages the file system database of the file name on
the recorded image and HDD's LBA (logical block
address) data. It is controlled by a command (file genera-
tion, retrieval, or detection) that is sent from the main CPU
through dual-port RAMs (IC401 and IC423).
The file system data base is kept saved in the SRAM
(IC406, IC407, IC414, IC415, IC421, IC422, IC432,
IC433) that are backed up by the lithium battery (BT401)
and a capacitor (C434).
The CPU (IC101) on the CCM-37A board controls the
network using the 10Base-T Ethernet controller (IC121).
IC101 sends a command to the main CPU through the
dual-port RAMs (IC801 and IC802) on the SY-283 board
when the file system is downloaded or uploaded.
Main CPU sends a command or receives a status to or from
each option board or HDD array (PU-113 board) through a
PCI controller (IC203) while exchanging commands or
status with each CPU above.
Receiving and sending data are performed using the
common memory (IC1018 to IC1021) that is shared by the
above described CPUs and the HDD array (PU-113 board).
For example, when a file is uploaded from a network, the
data is written into the common memory from the CCM-
37A board. This data is read out from the common
memory by the HDD array (PU-113 board) via the PCI
controller.
6-1 (E)
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