NEC mPD98409 Q&A page 8

CHAPTER 6 TRANSMISSION SCHEDULER ........................................................................................20
Q.6.1 What is the relationship between the scheduler register settings (I, M, and P parameters) and
the actual transmission rate?
Q.6.2 Is the same cell scheduling operation performed with scheduler register settings of I/M = 1/10 and
I/M = 10/100?
Q.6.3 Is it possible to make the priorities of two or more shapers the same?
Q.6.4 Is it possible to control the band between VCs (for example, widen the cell transmission interval
between VC1 and VC2)?
Q.6.5 What is the time set for transmitting one cell in cell transmission scheduling?
Q.6.6 What is the relationship between cell transmission scheduling and DMA operations?
Q.6.7 Does the host CPU have to set the A bit of the scheduler register?
CHAPTER 7 TRANSMISSION .................................................................................................................23
Q.7.1 Is it possible for the transmit FIFO to overflow and for cells to be discarded?
Q.7.2 Is there a limit to the size of the transmit queue of each VC configured with a transmit packet
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descriptor?
Q.7.3 How is transmission performed if SIZE = 0 is set for an AAL-5 transmit packet descriptor?
If a transmit queue consists of a valid packet descriptor → link pointer → blank packet descriptor
Q.7.4
sequence, to what does the Tx queue read pointer of the transmit VC table point on completion of
transmission?
Q.7.5 Can a packet be added during transmission when the transmit VC is active?
Q.7.6 When are the contents of packet descriptor Word0 stored in transmit VC table Word0?
Q.7.7 Is there a limit to the number of VCs linked to a shaper?
Q.7.8 Is there any problem if the value of the vacant field (Word1, Word2 bits 31 to 16)
of the transmit packet descriptor is not 0? Are the values on the system memory rewritten?
Q.7.9 Is there any problem if the value of the vacant field (Word1, Word2 bits 31 to 16)
of the transmit buffer descriptor is not 0? Are the values on the system memory rewritten?
Q.7.10 What does the Packet queue pointer field for transmission indication indicate?
Q.7.11 How can the OAM F5 cell be transmitted?
CHAPTER 8 RECEPTION........................................................................................................................28
Q.8.1 What will happen if a VPI/VCI value cell not enabled by the receive lookup table has been received,
and is it reported?
Q.8.2 How is a CRC-10 error reported when a Raw cell is received? Is it possible
to disable error checking?
Q.8.3 Is there a limit to the number of batches in the receive pool?
Q.8.4 Is it possible to temporarily stop reception for each VC?
Q.8.5 Are there cases in which a receive batch is consumed even if a receive indication that
includes error information has been reported?
Q.8.6 Is only the user data of AAL-5 CPCS-PDU stored in the receive buffer when an AAL-5 packet is
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received?
Q.8.7 How should the T1 time register (T1R) be set to detect a T1 error?
Q.8.8 Can the receive pool for Raw cells be shared with the receive pool for AAL-5?
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