12 CPCI3UX606
1.4.9 P9 and P10 (ETH1/GPIO/COM1 Options)
P9 and P10 must both be linked as appropriate for the IMP3A build option, as
shown in Figure 1‐3.
Figure 1-3 Connection Options
Table 1-13 P9 Pin Assignments
Pin
Signal
1
ETH1_3+
3
ETH1_3+_GPIO10_COM1_CTS 4
5
GPIO10
Table 1-14 P10 Pin Assignments
Pin
Signal
Pin Signal
2
ETH1_3-
3
COM1_RTS 4
ETH1_3-_GPIO11_COM1_RTS
6
GPIO11
1.4.10 J3 (10/100/1000BaseT Ethernet Channel 0)
Gigabit operation depends on availability of the required signals, which is an
IMP3A build option (see also P1). 10/100 signals are given in parentheses.
Table 1-15 J3 Pin Assignments
Pin
Signal
1
ETH0_0+ (TX+)
2
ETH0_0- (TX-)
3
ETH0_1+ (RX+)
4
ETH0_2+
5
ETH0_2-
6
ETH0_1- (RX-)
7
ETH0_3+
8
ETH0_3-
Pin Signal
COM1_CTS
Publication No. CPCI3UX606-HRM/1