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A D D - O N
F P G A
On the remaining 6 FPGA User programmable pins there is an ouput only, 6bit
port:
(1) Port data register
OPDR
7
Address:D7
EN
H
When the "EN" bit is set to "0", the OP0-5 pins are tristated. When the "EN" bit
is set to "1", the pins work as outputs of the register.
The pinout for add-on ports is following:
P00 1
P02 3
P04 5
P06 7
P10 9
P12 11
P14 13
P16 15
P20 17
P22 19
VCC 21
P24 23
P26 25
P30 27
P32 29
P34 31
P36 33
OP0 35
OP2 37
OP3 39
R/W for I/O ports means the following:
Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch, but not to the pin.
O U T P U T - O N L Y
6
5
4
3
OP5
OP4
OP3
OP2
2 P01
4 P03
6 P05
8 P07
10 P11
12 P13
14 P15
16 P17
18 P21
20 P23
22 GND
24 P25
26 P27
28 P31
30 P33
32 P35
34 P37
36 OP1
38 OP3
40 OP5
64
64
64
64
P O R T
2
1
0
OP1
OP0
---
Initial
Access
value
00
W
H
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