Sony AVD-S50 Service Manual page 30

AVD-S50/S50ES
Pin No. Pin Name
53 XSRQ
54 HINT
55 XS16
56 HA1
57 XPDI
58 VDDS
59, 60 HA0, HA2
61 VSS
62, 63 HCS0, HCS1
64 VDD
65 DASP
66 to 69 MDB0 to MDB3
70 VSS
71 MDB4
72 VDD5V
73 to 75 MDB5 to MDB7
76 XMWR
77 VDD
78 XRAS
79, 80 MA0, MA1
81 VSS
82 to 87 MA2 to MA7
88 VDD
89 MA8
90 VSS
91 MA9
92 MNT1
93 MNT2
94 XMOE
95 XCAS
96, 97 MDB8, MDB9
98 VSS
99 MDBA
100 VDD
101, 102 MDBB, MDBC
103 VDD5V
104 to 106 MDBD to MDBF
107 GFS
108 VSS
109 APEO
110 VDD
111 DASYO
112 GNDA5
113, 114 ASF1, ASF2
115 DASY1
30
I/O
DVD mode: Serial data request signal input from the DVD system processor
I
SACD mode: Serial data request signal input from the DSD decoder
O Not used. (Fixed at "H" in this set.)
O Not used. (Fixed at "H" in this set.)
I Not used. (Fixed at "H" in this set.)
I/O Not used. (Fixed at "H" in this set.)
— Power supply terminal (+5 V) (digital system)
I Not used. (Fixed at "H" in this set.)
— Ground terminal (digital system)
I Not used. (Open)
— Power supply terminal (+3.3 V) (digital system)
I/O Not used. (Fixed at "H" in this set.)
I/O Two-way data bus with the D-RAM
— Ground terminal (digital system)
I/O Two-way data bus with the D-RAM
— Power supply terminal (+5 V)
I/O Two-way data bus with the D-RAM
O Write enable signal output to the D-RAM
— Power supply terminal (+3.3 V) (digital system)
O Row address strobe signal output to the D-RAM
O Address signal output to the D-RAM
— Ground terminal (digital system)
O Address signal output to the D-RAM
— Power supply terminal (+3.3 V) (digital system)
O Address signal output to the D-RAM
— Ground terminal (digital system)
O Address signal output to the D-RAM
O EEPROM ready signal output to the mechanism controller
O Operation clock signal output for PSP physical disc mark detection to DSD decoder
O Output enable signal output to the D-RAM
O Column address strobe signal output to the D-RAM
I/O Two-way data bus with the D-RAM
— Ground terminal (digital system)
I/O Two-way data bus with the D-RAM
— Power supply terminal (+3.3 V) (digital system)
I/O Two-way data bus with the D-RAM
— Power supply terminal (+5 V)
I/O Two-way data bus with the D-RAM
O Guard frame sync signal output to the mechanism controller
— Ground terminal (digital system)
O Absolute phase error signal output
— Power supply terminal (+3.3 V) (digital system)
O RF binary signal output
— Ground terminal (analog system)
— Filter connected terminal for selection the constant asymmetry compensation
I Analog signal input after integrated the RF binary signal
Pin Description