Sony STR-DN840 Service Manual page 65

Pin No. Pin Name
133 VDD_INT
134 IRQ/GPIO
135 FLAG1
136 FLAG2
137 MLBCLK
138 FLAG3
139 MLBDAT
140 MLBDO
141 VDD_EXT
142 MLBSIG
143 VDD_INT
144
TRST
145 MLBSO
146 EMU
147 to
DATA0 to DATA3
150
151 TDO
152 DATA4
153 VDD_EXT
154, 155 DATA5, DATA6
156 VDD_INT
157 DATA7
158 TDI
159 SDCLK
160 VDD_EXT
161 to
DATA8 to DATA10
163
164 TCK
165 to DATA11, DATA12,
168 DATA14, DATA13
169 VDD_INT
170 DATA15
171 SDWE
172 SDRAS
173 RESET
174 TMS
175 SDCAS
176 VDD_INT
I/O
- Power supply terminal (+1.2V) (for core)
O Interrupt request signal output to the main system controller
I Error signal input terminal
I Non-LPCM setting signal input terminal
I Not used
O Error signal output to the main system controller and DSP2
I Not used
I Not used
- Power supply terminal (+3.3V) (for I/O)
I Not used
- Power supply terminal (+1.2V) (for core)
I Test reset signal input terminal (for JTAG)
I Not used
O Emulation status signal output terminal
I/O Two-way data bus with the SD-RAM
O Test data output terminal (for JTAG) Not used
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+3.3V) (for I/O)
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.2V) (for core)
I/O Two-way data bus with the SD-RAM
I Test data input terminal (for JTAG)
O Clock output terminal Not used
- Power supply terminal (+3.3V) (for I/O)
I/O
Two-way data bus with the SD-RAM
I
Test clock signal input terminal (for JTAG)
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.2V) (for core)
I/O Two-way data bus with the SD-RAM
O Write enable signal output to the SD-RAM
O Row address strobe signal output to the SD-RAM
I Reset signal input from the main system controller
I Test mode selection signal input terminal (for JTAG)
O Column address select signal output to the SD-RAM
- Power supply terminal (+1.2V) (for core)
Description
Not used
Not used
Not used
Not used
"L": reset
Not used
STR-DN840
65