Pioneer PRA-BD11 Service Manual page 75

Sdi aes/ebu input board, sdi aes/ebu output board
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5
Block Diagram - EDH and Data Core Processing
10
FRAMED
DATA [9:0]
VBLANKS/L
FLYWDIS
HVF
FLYWHEEL
5
H, V, F
TRS_ ERROR
COMPARE
BLANK_EN CLIP_TRS
Pin Descriptions
NUMBER
SYMBOL
6, 7
SDI, SDI
10, 11
SCI, SCI
15
HOSTIF_MODE
16
FIFOE/S
17
CRC_MODE
18 - 20
P[7:5]
21
SCL/P4
22
SDA/P3
23 - 25
A[2:0]/P[2:0]
26
R/W
5
6
EDH FLAG
EXTRACTION
CRC
COMPARISON/
CALCULATION
ANCILLARY
CHECKSUM
CALCULATION/
COMPARISON
TRS
DETECTION
ANCILLARY
CHECKSUM
TRS
CORRECTION
ITU-R-601 CLIPPING
TRS BLANKING
TRS INSERTION/
CORRECTION
TYPE
I
Differential serial data inputs.
I
Differential serial clock inputs.
I
Host interface mode select. When HIGH, the host interface is configured for I≤C mode. When
LOW, the host interface is configured for parallel port mode.
I
FIFO_RESET pulse control. When HIGH, the output FIFO_RESET pulse occu rs on the EAV
word. When LOW, the output FIFO_RESET pulse occurs on the SAV word.
I
CRC_MODE enable. When HIGH, CRC_MODE is enabled. When LOW, CRC_MODE is
disabled.
I/O
In parallel port mode, these are bits 7:5 of the host interface address/data bus. In I≤C mode,
these pins must be set LOW.
I/O
In parallel port mode, this is bit 4 of the host interface address/data bus. In I≤C mode, this is the
serial clock input for the I≤C port.
I/O
In parallel port mode, this is bit 3 of the host interface address/data bus. In I≤C mode, this is the
serial data pin for the I≤C port.
I/O
In parallel port mode, these are bits 2:0 of the host interface address/data bus. In I≤C mode,
these are input bits which define the I≤C slave address for the device.
I
Parallel port read/write control. When HIGH, the parallel port is configured as an output (read
mode). When LOW, the parallel port is configured as an input (write mode). In I≤C mode, this
pin must be set HIGH.
6
7
HOSTIF_MODE
FLAG_MAP
HOST INTERFACE/
FLAG PORT
ERRORED
FLAGS
FIELD
COUNTER
ERROR FLAGS
&
FORMAT PACKET
NEW CRC
10
CALCULATION
DESCRIPTION
PRA-BD11
7
8
I≤C
INTERFACE
DEDICATED
FLAG PORT
8-BIT
PARALLEL
INTERFACE
BYPASS_EDH
10
10
DOUT[9:0]
MUX
CRC_MODE
I≤C is a registered
Trademark of Philips
10
8
A
B
C
D
E
F
75

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