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3.6.2 Features
[ MCP ]
• Operation Temperature
- -30
o
C ~ 85
o
C
• Package
- 130-ball FBGA - 8.0x9.0mm
- Lead & Halogen Free
[ NAND Flash ]
• OPEN NAND FLASH INTERFACE(ONFI) 1.0
COMPLIANT
• POWER SUPPLY VOLTAGE
-VCC/VCCQ = 1.7V ~ 1.95V
-MEMORY CELL ARRAY (with SPARE)
- Page size : (1K+32spare) words
- Block size : (64K+2K) words
- Plane size : 1024blocks
- Device size : 1024blocks
• PAGE READ / PROGRAM TIME
- Random Read Time(tR) : 25us(Max)
- Sequential access time : 45ns(Min)
- Page program : 300us(Typ)
• BLOCK ERASE
- Block Erase Time : 3ms(Typ.)
• COMMAND SET
- ONFI1.0 Compliant command set
- Read Unique Ids
• ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
- 3rd cycle: Internal chip number, Cell Type,
Number of Simultaneously
Programmed Pages
- 4th cycle: Page size, Block size, Organization,
Spare size
• RELIABILITY
- 50,000 Program / Erase cycles
(with 4bit/512+16 Byte ECC)
• DATA RETENTION
- 10 years
LGE Internal Use Only
LGE Internal Use Only
, 1.0t, 0.65mm pitch
2
3. TECHNICAL BRIEF
[ DDR SDRAM ]
•Standard SDRAM Protocol
•Clock Synchronization Operation
•Multibank Operation : Internal 4 Bank Operation
•VDD / VDDQ = 1.7V to 1.95V
•Memory Cell Array
- 4Mb x 4Bank x 16 I/O
•LVCMOS Compatible I/O Interface
•Programmable Burst Length
- 1, 2, 4, 8 or full page
•Programmable Burst Type
- sequential or interleaved
•Programmable CAS Latency
•Programmable Drive Strength
Copyright © 2007 LG Electronics. Inc. All right reserved.
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Copyright © 2013 LG Electronics. Inc. All right reserved.
3. TECHNICAL BRIEF
Only for training and service purposes
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