Main(Pre/Rec) Schematic Diagram - JVC GR-DA30UC Schematic Diagrams

MAIN(PRE/REC) SCHEMATIC DIAGRAM

0 1 MAIN(PRE/REC)
TO MAIN IF(CN111),
HID
CPU,PARAGON3
PBH
TO CPU
RECH
TO MAIN IF(CN111)
ENV_OUT
TO MAIN IF(CN111). ATFI
PARAGON3
AGC_CTL
DUMP_CTL
ATF_GAIN
TO PARAGON3
NOSIG_LV
REC_ADJ
REC_CTL
VREF_1.1
TO PARAGON3
AGC_OUT
VRB_AGC
VRB_ATF
TO MAIN IF(CN111).
ATFI
PARAGON3
REC_DATA
TO PARAGON3
REC_CLK
L3505 NQR0602-001X
R3530
0Ω
L3502 OPEN
REG_4.65V
REG_4.65V
L3504 OPEN
L3501 NQR0602-001X
REG_2.8V
REG_2.8V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
All manuals and user guides at all-guides.com
REG_4.65V_L3505
REG_4.65V_L3504
REG_2.8V_L3501
(No.YF219)2-15
C3508
470p
C3509
470p
36 35 34 33 32 31 30 29 28
PB_OUT
37
C3510
0.01
C3511
68pF PB_IN
38
C3512
0.01
AGC_CTL
39
C3513 AGC_DET
40
0.01
C3514
0.01
Vcc4.8
OPEN
41
AGC_OUT
42
IC3501
MAIN_GND
43
LA70054W
C3515 0.01
OPEN
REG_1.1V
44
C3516 0.01
VRB_AGC
45
C3517 0.01
VRB_ATF
46
C3518 0.01
ATF_GAIN
47
REG_FIL
C3519
48
0.1
R3535
470k
OPEN
1 2 3 4 5 6 7 8 9
2-16(No.YF219)
27 26 25
HEAD_GND
24
R3509
DX2 150
23
X2
22
Y2
21
R3508
DY2 150
20
HEAD_GND
19
C3504
HEAD_VCC 0.01
18
HEAD_GND
17
R3507
DX1 150
16
X1
15
Y1
14
R3506
DY1
150
13
10 11 12
R3519
OPEN
R3518
OPEN
yf219_y20444001a_rev0.1
GND
1F
1S
GND
TO MAIN IF
(CN3501)
GND
2F
2S
GND