Advertisement
5
+3.3V_I/O
+5V_IN
+3.3V_I/O
M_SCL
R51
R50
R49
M_SDA
10K/6
56R/6F
NC/ 0R/6
R52
JTAG
56R/6F
I2C address:
R53
A0H and
R54
56R/6F
A1H
NC/ 10K/6
R56
R57
R55
U4
56R/6F
22/6
22/6
8
1
VCC
A0
G ND
7
2
WP
A1
G ND
6
3
SCK
A2
5
4
SI
VSS
24LC32-SN
R50 & R54 TO
D
SOIC8
BE OPENED FOR
GND
JTAG ENABLE.
1
SCART-1-OUT_CVBS
+3.3V_LBADC
+5V_IN
+3.3V_I/O
R60
R61
4.7K/6
NC/75R/6F
R64
Q3
R62
R63
+3.3V_I/O
GPIO13/PWM2
2
CH3904
100R/6
10K/6
0R/6
Q4
R67
2N7002E
R68
47/6
R236
LED CONTROL
2
NC/ 0R/6
10K/6
LED_G
R69
+3.3V_LBADC
100R/6
+5V_IN
G ND
GPIO9/SIPSCL
R76
4.7K/6
R77
Q5
C N4
GPIO12/PWM1
2
CH3904
1
0R/6
TXD/JTMODE
2
RXD/JTCLK
3
4
R79
47/6
HEADER 4
GPROBE
LED_O
C
IR AND KEYPAD
+5V_IN
CONNECT PORT
D6
D7
D8
BAV99L
BAV99L
BAV99L
+3.3V_LBADC
3
3
3
+5V_IN
C35
C36
C37
NC/10pF
NC/10pF
NC/10pF
R81
R82
1K/6
1K/6
G ND
G ND
C N5
R83
FUSE_1A/6
1
1:5V
func tion key
R84
0R/6
AD C_IN1
2
2:AD KEY
power key
R85
0R/6
AD C_IN2
3
3:PWR KEY
4
R86
0R/6
LED_O
4:GND
5
5:LED_R
R87
0R/6
LED_G
6
6:LED_G
I R
R88
0R/6
GPIO6/IR
7
7:IR
7P _2mm
R89
R90
G ND
+5V_IN
NC/ 10kF
NC/ 10kF
G ND
D9
D10
D11
BAV99L
BAV99L
BAV99L
3
3
3
AD C_IN1
C41
C42
C43
C44
NC/10pF
NC/10pF
NC/10pF
0.1uF/6
AD C_IN2
C45
RESERVE
G ND
0.1uF/6
B
CN12
func tion key
1
power key
2
+3.3V_LBADC
3
R102
HEADER 4
AD C_IN3
1
LBADC_IN3
G ND
0R/6
C46
R104
ADC_IN3_RET
0.1uF/6
R105
10K/6
AD C_IN4
1
DET_SCART-COMP
+3.3V_LBADC
0R/6
C47
ADC_IN4_RET
0.1uF/6
R111
AD C_IN5
C48
NC/ 10K/6
ADC_IN5_RET
0.1uF/6
R122
AD C_IN6
NC/ 10K/6
C50
R123
100R/6
R124
100R/6
ADC_IN6_RET
0.1uF/6
SW*2 SELECT
(Optional)
G ND
+1.8V_CORE
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
22uF/25V
22uF/25V
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
G ND
+3.3V_RPLL
+3.3V_LBADC
+3.3V_ADC
+3.3VSC_ADC
+3.3VC_ADC
A
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
G ND
G ND
GND
GND
G ND
+3.3V_I/O_HUDSON
+3.3V_LVDS_OUT
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
22uF/25V
22uF/25V
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
0.1uF/6
22uF/25V
0.1uF/6
0.1uF/6
0.1uF/6
GND
G ND
5
4
+3.3V_RPLL
+3.3V_LBADC
+1.8V_ADC
+3.3V_ADC
+1.8V_CORE
+3.3VSC_ADC
+1.8V_RPLL
C28
0.1uF/6
A_RETURN
A_RET
C29
0.1uF/6
B_RETURN
B_RET
C30
0.1uF/6
C_ RETURN
C_RET
C31
0.1uF/6
D_ RETURN
SV_RET
168
2
A1
A1P
TP1
178
A2P
+5V_IN
188
1
A3
A3P
198
1
A4
A4P
174
A_RET
AN
170
2
B1
B1P
R58
R59
TP2
180
B2P
190
1
B3
B3P
NC/22/6
NC/12K/6
200
1
B4
B4P
184
B_RET
BN
172
2
C1
C1P
Q2
TP3
182
C2P
2
192
1
C3
C3P
202
C4P
CH3904
TP4
194
C_RET
CN
166
1
SV1
SV1P
176
1
SV2
SV2P
186
1
SV3
SV3P
R65
R66
196
1
SV4
SV4P
204
SV_RET
SVN
NC/1K/6
NC/22K/6
HUDSON
C32
162
ADC_TEST
VOUT
206
FLI8125
VOUT2
205
VO_GND
NC/0.1uF/6
G ND
H S1
156
U3
HSYNC1
G ND
VS1
157
+5V_IN
VSYNC1
R74
R75
AD C_IN1
2
LBADC_IN1
4.7K/6
4.7K/6
AD C_IN2
3
LBADC_IN2
AD C_IN3
4
LBADC_IN3
AD C_IN4
5
LBADC_IN4
+5V_IN
AD C_IN5
6
LBADC_IN5
AD C_IN6
7
LBADC_IN6
R78
NC/ 0R/6
RET
8
GND
LBADC_RTN
20
TEST
GPIO15/TM1
21
GPIO15
JTAG
22
JTAG_BS_EN
23
SCART16
R80
NC/ 0R/6
25
HOST_SDATA
G ND
24
HOST_SCLK
VGA_SCL
26
2
VGA_SCL
DDC_SCLK
VGA_SDA
27
2
VGA_SDA
DDC_SDATA
8125_SDA
31
MSTR_SDATA
+3.3V_RPLL
+3.3V_RPLL
8125_SCL
30
MSTR_SCLK
C33
C34
XTAL
15
XTAL
19.6608MHz
TCLK
16
TCLK
SC22pF
X1
SC22pF
13
VBUFC_RPLL
GPIO0/LED1
34
TCK
GPIO1/LED2
35
TDI
C38
GPIO2/PWR
36
TMS
22uF/25V
GPIO3/SCRT16_1
37
TRST
GPIO6/IR
38
GPIO6/IRin
GPIO7/IRQ
41
GPIO7/IRQin
GPIO8/IRQOUT
42
GPIO8/IRQout
GPIO9/SIPSCL
43
GPIO9/SIPC_SCLK
GPIO10/SIPSDA/A18
44
GPIO10/SIPC_SDATA/A18
GPIO11/PWM0
47
GPIO11/PWM0
GPIO12/PWM1
48
GPIO12/PWM1
GPIO13/PWM2
51
GPIO13/PWM2
+5V_IN
GPIO14/PWM3
52
GPIO14/PWM3/SCART16
R91
TDO
55
TDO
10K/6
/RESET
10
RESETn
+
C39
NC/ 33uF/25V
C40
NC/ 0.01uF/6
159
NC
G ND
G ND
GND
G ND
GPIO15/TM1
4
CSRAM
R93
0R/6
PWM0
GPIO11/PWM0
5
PWM0
R103 0R/6
TDO
7
PROTN_138
+5V_IN
R106
R107
R108
R109
R110
10K/6
10K/6
10K/6
10K/6
10K/6
GPIO0/LED1
2
VGA_DET
GPIO1/LED2
2
S-EDID
R125 0R/6
S TANDBY
GPIO8/IRQOUT
8
STANDBY
R127 0R/6
GPIO2/PWR
7
S-AMP_MUTE
G ND
R128 0R/6
GPIO3/SCRT16_1
7
S-AMP_SLEEP
2
+1.8V_ADC
+1.8V_RPLL
2
C62
C63
C64
C65
C66
C67
22uF/25V
0.1uF/6
0.1uF/6
0.1uF/6
22uF/25V
0.1uF/6
6
G ND
G ND
6
+3.3VB_ADC
+3.3VA_ADC
+5V_IN
C78
C79
C80
C81
C82
C83
0.1uF/6
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
0.1uF/6
G ND
G ND
GND
+3.3V_LVDS
+3.3V_I/O
1
PWM3-GPIO14-FB
C95
C96
C97
C98
22uF/25V
0.1uF/6
22uF/25V
0.1uF/6
G ND
G ND
G ND
GND
4
3
+3.3VC_ADC
+3.3VB_ADC
+3.3V_LVDS
+3.3VA_ADC
+3.3V_I/O_HUDSON
+3.3V_LVDS_OUT
～
RN1
RN6 to be very close to CN8 and placed enroute
trace to avoid stub on the LVDS lines and also to have a very
small stub on the digital lines
R N1
PD20/B4
8
1
33R
PD21/B5
7
2
PD23/B7
PD22/B6
89
6
3
PD23/B7/GPIO3
PD22/B6
PD23/B7
88
5
4
PD22/B6/GPIO2
PD21/B5
87
PD21/B5/GPIO1
PD20/B4
TXB1+
R N2
33R
DEBLU0
86
8
1
PD20/B4/GPIO0
TXB1-
DEBLU1
7
2
TXB0-
TXB0+
DEBLU2
81
6
3
CH0N_LV_O/B3
80
TXB0+
TXB0-
5
4
DEBLU3
CH0P_LV_O_B2
79
TXB1-
R N3
CH1N_LV_O_B1
78
TXB1+
TXBC+
8
1
33R
D EGRN4
CH1P_LV_O_B0
77
TXB2-
TXBC-
7
2
D EGRN5
CH2N_LV_O_G7
76
TXB2+
TXB2+
6
3
D EGRN6
CH2P_LV_O_G6
75
TXBC-
TXB2-
5
4
D EGRN7
CLKN_LV_O_G5
74
TXBC+
R N4
CLKP_LV_O_G4
TXB3-
TXA0+
33R
D EGRN0
73
8
1
CH3N_LV_O_G3
TXB3+
TXA0-
D EGRN1
72
7
2
CH3P_LV_O_G2
TXB3+
D EGRN2
6
3
TXB3-
D EGRN3
5
4
TXA0-
69
CH0N_LV_E/G1
TXA0+
R N5
68
CH0P_LV_E/G0
TXA1-
TXA2+
33R
DE RED4
67
8
1
CH1N_LV_E/R7
66
TXA1+
TXA2-
7
2
DE RED5
CH1P_LV_E/R6
65
TXA2-
TXA1+
6
3
DE RED6
CH2N_LV_E/R5
64
TXA2+
TXA1-
5
4
DE RED7
CH2P_LV_E/R4
63
TXAC-
R N6
CLKN_LV_E/R3
62
TXAC+
TXA3+
8
1
33R
DE RED0
CLKP_LV_E/R2
61
TXA3-
TXA3-
7
2
DE RED1
CH3N_LV_E/R1
TXA3+
TXAC+
DE RED2
60
6
3
CH3P_LV_E/R0
TXAC-
DE RED3
5
4
57
VCO_LV
SMT test vias placed close to each other
DCLK/VOPCLK
93
DCLK
91
DHS/VOP_HS
DHS
92
DVS/VOP_VS
DVS
90
DEN/VOP_FLD
DEN
153
VID_CLK_1
122
GPIO4/VIDIN_HS
121
GPIO5/VIDIN_VS
GPIO19/VBID0/A3/PD27
135
VID_DATA_IN_0
GPIO18/VBIVAL/A2/PD26
136
VID_DATA_IN_1
GPIO17/VBICLK/A1/PD25
137
VID_DATA_IN_2
GPIO16/VIDFLD/A0/PD24
138
VID_DATA_IN_3
139
VID_DATA_IN_4
140
GPIO23/VBID4/A7/PD31
VID_DATA_IN_5
141
GPIO22/VBID3/A6/PD30
VID_DATA_IN_6
142
GPIO21/VBID2/A5/PD29
VID_DATA_IN_7
GPIO20/VBID1/A4/PD28
145
VID_D8/GPIO16
VID_DATA_IN_8/GPIO16
146
VID_DATA_IN_9/GPIO17
RESET_AUDIO 6
147
VID_DATA_IN_10/GPIO18
OSDFLD/A11/PD35/JT_BSCAN
148
VID_DATA_IN_11/GPIO19
VBI_D7/A10/PD34/BT2
149
VID_DATA_IN_12/GPIO20
VBI_D6/A9/PD33/BT1
150
VID_DATA_IN_13/GPIO21
VBI_D5/A8/PD32/BT0
151
VID_DATA_IN_14/GPIO22
152
VID_DATA_IN_15/GPIO23
EXTCLMP/A15/SPIEN
123
VID_D16/D0/PD39
OSDCLK/A14/PD38/OPMD1
VID_DATA_IN_16/PD39/VID2_D0
124
VID_D17/D1/PD40
OSDHS/A13/PD37/OPMD0
VID_DATA_IN_17/PD40/VID2_D1
125
VID_D18/D2/PD41
OSDVS/A12/PD36/ROM512K
VID_DATA_IN_18/PD41/VID2_D2
128
VID_D19/D3/PD42
VID_DATA_IN_19/PD42/VID2_D3
129
VID_D20/D4/PD43
VID_DATA_IN_20/PD43/VID2_D4
130
VID_D21/D5/PD44
VID_DATA_IN_21/PD44/VID2_D5
VID_D22/D6/PD45
131
VID_DATA_IN_22/PD45/VID2_D6
VID_D23/D7/PD46
132
VID_DATA_IN_23/PD46/VID2_D7
ROM_SCLK/A17/OSC_SEL
VID_CLK2/ROM_OEN/PD47
ROM_SDO/A16/OCM_ROM
118
VID_CLK2/ROM_OEN/PD47
ROM_SDI/WEN
SIPSDA/A18
97
ROM_SDI/ROM_WEN
SCSN/ROMCS
ROM_SDI/WEN
94
ROM_SCSN/ROM_CSN
VID_D16/D0/PD39
115
GPIO16/VIDFLD/A0/PD24
VID_D17/D1/PD40
VID_DE/FLD/A0/PD24
114
GPIO17/VBICLK/A1/PD25
VID_D18/D2/PD41
A1/PD25
113
GPIO18/VBIVAL/A2/PD26
VID_D19/D3/PD42
A2/PD26
112
GPIO19/VBID0/A3/PD27
A3/PD27
111
GPIO20/VBID1/A4/PD28
VID_D20/D4/PD43
A4/PD28
GPIO21/VBID2/A5/PD29
VID_D21/D5/PD44
110
A5/PD29
GPIO22/VBID3/A6/PD30
VID_D22/D6/PD45
109
A6/PD30
GPIO23/VBID4/A7/PD31
VID_D23/D7/PD46
108
A7/PD31
VBI_D5/A8/PD32/BT0
107
A8/PD32
VBI_D6/A9/PD33/BT1
VID_CLK2/ROM_OEN/PD47
106
A9/PD33
VBI_D7/A10/PD34/BT2
SCSN/ROMCS
105
A10/PD34
OSDFLD/A11/PD35/JT_BSCAN
104
XOSD_FLD/A11/PD35
103
OSDVS/A12/PD36/ROM512K
XOSD_VS/A12/PD36
102
OSDHS/A13/PD37/OPMD0
XOSD_HS/A13/PD37
101
OSDCLK/A14/PD38/OPMD1
XOSD_CLK/A14/PD38
100
EXTCLMP/A15/SPIEN
ADC_CLMP/A15
96
ROM_SDO/A16/OCM_ROM
ROM_SDO/A16
ROM_SCLK/A17/OSC_SEL
95
ROM_SCLK/A17
PPWR
54
PPWR
PPWR
5
PBIAS
53
PBIAS
PBIAS
5
+3.3V_I/O
BT0
BT1
R94
R95
R96
G ND
NC/ 10K/6
NC/ 10K/6
OCMADDR8
+3.3V_I/O_HUDSON
OCMADDR9
OCMADDR10
U5
OCMADDR12
2
GND
/RESET
1
RESET#
3
VCC
R112
R113
NC/ MAX809MEUR-T-U
C49
NC/ 0.01uF/6
10K/6
10K/6
G ND
G ND
H S1
A_HS
VS1
A_VS
R136 22/6
M_SDA
8125_SDA
M_SDA
M_SCL
R138 22/6
8125_SCL
VID_D8/GPIO16
M_SCL
U6
+5V_IN
R92
0R/6
1
16
2Y1
VCC
GPIO10/SIPSDA/A18
SIPSDA/A18
2
15
2Y0
2Z
TXD/JTMODE
3
14
3Y1
1Z
VGA_SDA
4
13
3Z
1Y1
5
12
3Y0
1Y0
6
11
E
S1
7
10
VEE
S2
R129 0R/6
8
9
GND
S3
GPIO14/PWM3
74HCT4053
G ND
R130
NC/ 10K/6F
CAN BE USED AS FAST
BLANK FOR SCART-2
G ND
3
2
on the
TXB3+
TXB3-
TXBC+
DEBLU[0..7]
DEBLU[0..7]
5
TXBC-
DEBLU4
DEBLU5
TXB2+
DEBLU6
DEBLU7
TXB2-
DEBLU3
TXB1+
DEBLU2
DEBLU1
TXB1-
DEBLU0
TXB0+
D EGRN7
D EGRN6
TXB0-
D EGRN5
D EGRN4
DEGRN[0..7]
TXA3+
DEGRN[0..7]
5
D EGRN3
D EGRN2
TXA3-
D EGRN1
D EGRN0
TXAC+
TXAC-
DE RED7
DE RED6
TXA2+
DE RED5
DE RED4
TXA2-
D ERED[0..7]
DE RED3
TXA1+
DERED[0..7]
5
DE RED2
DE RED1
TXA1-
DE RED0
TXA0+
TXA0-
R70
22/6
DC LK
DCLK
5
R71
0R/6
D HS
D HS
5
R72
0R/6
D VS
DVS
5
R73
0R/6
D EN
D EN
5
R N7
OCMADDR[0..18] 4
33R
OCMADDR3
8
1
OCMADDR2
7
2
OCMADDR1
6
3
OCMADDR0
5
4
R N8
8
1
33R
OCMADDR7
7
2
OCMADDR6
6
3
OCMADDR5
5
4
OCMADDR4
R N9
33R
OCMADDR11
8
1
OCMADDR10
7
2
OCMADDR9
6
3
OCMADDR8
5
4
RN10
8
1
33R
OCMADDR15
7
2
OCMADDR14
6
3
OCMADDR13
5
4
OCMADDR12
OCMADDR17
OCMADDR16
OCMADDR18
ROM_WEN
ROM_WEN
4
RN11
33R
8
1
7
2
6
3
5
4
OCMDATA[0..7] 4
RN12
8
1
33R
OCMDATA0
7
2
OCMDATA1
6
3
OCMDATA2
5
4
OCMDATA3
RN13
8
1
33R
OCMDATA4
OCMDATA5
7
2
OCMDATA6
6
3
1-2
OCMDATA7
5
4
BT0
RN14
33R
ROM_OEN
8
1
ROM_OEN
4
ROM_CSN
3-4
7
2
ROM_CSN
4
6
3
5
4
BT1
5-6
BT2
7-8
9-10
11-12
BT2
OP_MODE0
OCM_ROM
ROM512K
OP_MODE1
ATMSF
13-14
15-16
R97
R98
R99
R100
R101
NC/ 10K/6
10K/6
NC/ 10K/6
NC/ 10K/6
NC/ 10K/6
NC/ 10K/6
OCMADDR7
BOOTSTRAP HEADER TO BE CHANGED AS PER NEW
OCMADDR16
OCMADDR14
OCMADDR13
R114
R115
R116
R117
R118
R119
ROM_SDO/A16/OCM_ROM
10K/6
NC/10K/6
10K/6
10K/6
10K/6
10K/6
ROM_SCLK/A17/OSC_SEL
G ND
+3.3V_I/O
ROM_SCLK/A17/OSC_SEL
R133
10K/6
R134 0R/6
GPIO16_AUDIO-SEL 6
+3.3V_I/O
+3.3V_I/O
VGA_SCL
#OPTIONAL
RXD/JTCLK
R139
R137
R137 TO BE
USED FOR
10K/6
NC/ 10K/6
BOUNDARY
SCAN
GPIO7/IRQ
OSDFLD/A11/PD35/JT_BSCAN
R141
G ND
R143 NC/ 0R/6
47K/6
I NTR
IRQ_IN USED FOR STANDBY
GND
G ND
2
1
TXB3+
5
TXB3-
5
TXBC+
5
LBADC'S
TXBC-
5
LBADC_IN1
KEYBOARD1
TXB2+
5
LBADC_IN2
KEYBOARD2
TXB2-
5
LBADC_IN3
SCART-1-IN_PIN8/EIAJ1
TXB1+
5
LBADC_IN4
SCART-2-IN_PIN8/EIAJ2
TXB1-
5
LBADC_IN5
EIAJ3
TXB0+
5
LBADC_IN6
FOR LDR( OPTION)
TXB0-
5
GPIO'S USED
TXA3+
5
GPIO0
BLUE CHANNEL BIT 4
TXA3-
5
GPIO1
BLUE CHANNEL BIT 5
TXAC+
5
GPIO2
BLUE CHANNEL BIT 6
TXAC-
5
GPIO3
BLUE CHANNEL BIT 7
TXA2+
5
GPIO4
DIGITAL VIDEO INPUT HS
TXA2-
5
GPIO5
DIGITAL VIDEO INPUT VS
TXA1+
5
GPIO6
IR DECODING
TXA1-
5
GPIO7
INTR/IRQ IN
TXA0+
5
STDBY / IRQOUT
GPIO8
TXA0-
5
GPIO9
SIPSCL
GPIO10
SIPSDA
GPIO11
PWM0-PANEL BACKLIGHT
GPIO12
PWM1- LED1
GPIO13
PWM2- LED2
GPIO14
PWM3- SCART-1-IN-FB/EIAJ SENSE
GPIO15
CHIP SELECT FOR FLASH/SRAM
GPIO16
FOR ROM ADDRESS/16-bit INPUT
GPIO17
FOR ROM ADDRESS/16-bit INPUT
GPIO18
FOR ROM ADDRESS/16-bit INPUT
GPIO19
FOR ROM ADDRESS/16-bit INPUT
GPIO20
FOR ROM ADDRESS/16-bit INPUT
GPIO21
FOR ROM ADDRESS/16-bit INPUT
GPIO22
FOR ROM ADDRESS/16-bit INPUT
GPIO23
FOR ROM ADDRESS/16-bit INPUT
LOW
OCM will RUN on FLCK
HIGH
OCM will RUN on TCLK
LOW & LOW
Run from External Rom if External ROM has a valid signature
LOW & HIGH
Forced to Run from Internal ROM
HIGH & LOW
Forced to Run from External ROM
HIGH & HIGH
Run from external ROM if external ROM has a valid signature and passes integrity checks
LOW
Parallel Flash / ROM is 256K
HIGH
Parallel Flash / ROM is 512K
LOW & LOW
Normal Operation. UART in 186 on systems pins. I2C to JTAG available on DDC2Bi pins
LOW & HIGH
I2C to JTAG Bridge; UART not available
HIGH & LOW
JTAG port 5 Wire-UART not available
HIGH & HIGH
External parallel control bus using ROM Address/Data
LOW
Internal ROM ON, and mapped to 64K of OCM address range. OCM boot will be from internal ROM code
HIGH
External parallel control bus using ROM Address/Data
LOW
For all other different Flashes
HIGH
For Atmel Serial Flash
R120 0R/6
ROM_SDO
ROM_SDO
4
R121 0R/6
ROM_SCLK
ROM_SCLK
4
+3.3V_I/O
R126
10K/6
ROM_SDI/WEN
SCSN/ROMCS
R132
R131
NC/ 47K/6
0R/6
G ND
ROM_SDI
ROM_SDI
R135
0R/6
SC SN
SCSN
+3.3V_I/O
#OPTIONAL
R140 TO BE USED
R140
FOR
NC/ 10K/6
SERIAL FLASH
EXTCLMP/A15/SPIEN
R142
AT2002 ,20" TV
10K/6
Title
G ND
MAIN CHIP：HUDSON
Size
Document Number
HUDSON PLATFORM
SCHEMATIC1
Date:
Monday, June 26, 2006
Sheet
3
1
D
C
B
4
A
4
R ev
B3C
o f
8
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