Absolute Maximum Ratings - Sharp RJ33N3AD0LT Specifications

OD1,OD2
OS1,OS2
φ φ
RS1, RS2
,φ ,φ
φ
V1A V1B
φ ,φ ,φ
V2 V3
,φ ,φ
φ
VS2 VS3
,φ ,φ
φ
LH1A H1A
φ ,φ ,φ
LH1B H1B
OFD
OOFD
PW
GND

4 ABSOLUTE MAXIMUM RATINGS

Output transistor drain voltage
Overflow drain voltage
Reset gate clock voltage
Vertical shift register clock voltage
Horizontal shift register clock voltage
Voltage difference between P_well and vertical clock
Voltage difference between vertical clocks
Storage temperature
Ambient operating temperature
(Note 1) Do not connect to DC voltage directly. When OFD is connected to GND, connect V
Overflow drain clock is applied below 22.5 Vp-p.
(Note 2) Do not connect to DC voltage directly. When φ
Reset gate clock is applied below 5.1 Vp-p.
(Note 3) When clock width is below 10 μs, and clock duty factor is below 0.1 %, voltage difference
between adjoining vertical clocks are guaranteed up to 15.4 V.
Do not change allφ
of V pulse.
VH
φ
Do not change directly into V
Symbol
,φ ,
V1C V1D
,φ φ ,
V4 VS1A VS1B
VS4
,
H2A
,
H2B
Parameter
during 0.5μs before rising edge of V
V
→V
VL
φ
RJ33N3AD0LG
Pin name
Output transistor drain
Output signals
Reset transistor clock
Vertical shift register clock
Horizontal shift resister clock
Overflow drain
Output overflow drain
P_well
Ground
Symbol
V
OD
V
OFD
V
RS
φ
V
V
φ
V
H
φ
V -V
PW V
φ
V -V
V V
φ φ
T
STG
T
OPR
is connected to GND, connect V
RS
VH
φ
or V →V .
VH VH VL
φ φ φ
Ratings
0 to +15.4
Internal output (Note 1)
Internal output (Note 2)
V to +15.4
PW
-0.3 to +5.1
-23.8 to +0
0 to +9.9 (Note 3)
-40 to +90
-30 to +85
to GND.
OD
to GND.
OD
pulse and after falling edge
5
=25℃）
（T
A
Unit
V
V
V
V
V
℃
℃