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AHIP6+ Advanced High Integration Platform ® with Pentium II Processor P/N 133172-001B Ó Ó Ó Ó 1998 XYCOM, INC. Printed in the United States of America...
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Windows is a registered trademark of Microsoft Corp. in the United States and other countries. Copyright Information This document is copyrighted by Xycom Incorporated (Xycom) and shall not be reproduced or copied without ex- pressed written authorization from Xycom. The information contained within this document is subject to change without notice. Xycom does not guarantee the accuracy of the information and makes no commitment toward keeping it up to date.
Product Overview The Xycom Advanced High-Integration Platform (AHIP6+) board is designed ex- pressly for use in Xycom’s line of flat panel industrial personal computers. The AHIP6+ is optimized in design, layout, and features for use with flat panel computer systems. This integrated design approach allows Xycom industrial PC/ATs to incor- porate “Big PC”...
PCI Local Bus Interface The Pentium design uses the 440BX chip set. The 440BX integrates a high perform- ance interface from PCI to IDE. This interface is capable of accelerated data transfers. The 440BX chipset provides an accelerated PCI-to-ISA interface that includes ·...
ID command. If you experience problems, change the PIO to standard. Expansion Options The AHIP6+ offers expansion when used in conjunction with a Xycom Plug-in Ex- pansion Backplane. This gives the user a total of six full length slots: ·...
POST (Power On Self Test). The enhanced IDE (EIDE) interface supports up to 2 hard drives. Hard drive inter- face is via the Xycom plug-in backplane or the on-board IDE controller.
Caution The higher the PIO mode, the shorter the cycle time. As the IDE cable length increases, this reduced cycle time can lead to erratic operation. The total IDE cable length must not exceed 18 inches. If two IDE drives are connected, they must not be more than six inches apart.
Hardware Specifications Table Chapter 1 -2. Hardware Specifications Characteristic Specification Power Specifications Typical Maximum +12V 90mA 112.5mA -12V 30mA 37.5mA CPU speed 266 MHz, 333 MHz, 350 MHz, and 400 MHZ PCI Super VGA Graphics Controller 640x480, 800x600, and 1024x768, 64K colors maximum resolution 2 MB video DRAM Serial Ports (2) COM1 is RS-232 or RS-485...
Chapter 2 – Installation This chapter provides information on configuring the AHIP6+ Processor Module. Pinouts for the connectors are located in Appendix C. Figure 2-1 illustrates the jumper and connector locations on the AHIP6+. BACKLIGHT FPGA INTERNAL LED IN INVERTER KEYPAD TOUCH KEYPAD...
AHIP6+ Manual Configuration Options Jumpers The following tables list AHIP6+ jumpers, their default positions and their functions. The jumpers marked “Access” are placed at the top of the board for easy customer access. Table 2- 1. AHIP6+ Jumpers Jumper Position Function Push button reset switch DISABLED (Access) Push button reset switch ENABLED...
Chapter 2 – Installation System Interrupts The following table describes the interrupts used on the AHIP6+. Table 2- 3. System Interrupts Interrupt Function IRQ0 System Timer IRQ1 Keyboard IRQ2 Cascade IRQ3 Serial Port* IRQ4 Serial Port* IRQ5 Parallel Port* IRQ6 Floppy Controller IRQ7 Parallel Port*...
AHIP6+ Manual DMA Mapping Table 2- 4. DMA Channels Function DMA0 Unused (Could be used for EPP/ECP parallel port option) DMA1 Unused DMA2 Floppy Controller DMA3 Unused (Could be used for EPP/ECP parallel port option) DMA5 Unused DMA6 Unused DMA7 Unused DMA channels 0-3 are 8-bit and DMA channels 5-7 are 16-bit.
SRAM control register (May be remapped based on I/O port 234h) 182-1EF Available 1F0-1F7 IDE Controller (AT Drive) 1F8-22F Available Xycom LED port Xycom Flash control register Xycom IO port control register 278-27F Parallel Port 2 (see Note 1) 280-2F7 Available 2F8-2FF Serial Port 2 (see Note 1) 300-36F Available 370-377 Alt.
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AHIP6+ Manual Hex Range Device 3B0-3BB mono mode video 3BC-3BF reserved for parallel port 3C0-3CF VGA registers (see Note 2) 3D0-3DF CHIPS flat panel & color mode registers 3E0-3EF Available 3F0-3F7 Primary Floppy disk controller 3F8-3FF Serial port 1 (see Note 1) PCI configuration address register (see Note 4) PCI configuration data register (see Note 4) Note 1...
Chapter 2 – Installation Registers The AHIP6+ contains five I/O ports: 231h, 233h, 234h, and a user-definable port (port 180/1h, 2E0/1h, 3E0/1h, or 300/1h). These ports are compatible with AHIP4+ and AHIP 6+. Register 231h – CPU LED Port Register 231h controls the LEDs and signals shown in the following table. Table 2- 7.
AHIP6+ Manual Register 234h - I/O Port Location Register 234h controls the I/O port location register shown in the following table. Table 2- 9. Register 234h - I/O Port Location Register Signal Result Reserved Reserved Reserved Reserved I/O range select I/O range select bit 0 I/O range select I/O range select bit 1...
Chapter 2 – Installation Offset Registers The following registers are located starting at the I/O location defined by register 234h. Table 2- 11. I/O Port Selection (Port Address) I/O port selection Port address 180h 2E0h 3E0h 300h Offset 0 Page Register for Programming (Port Address) Offset 0 is a read-only register that checks the battery status Table 2- 12.
AHIP6+ Manual Offset 1 Page Register for Programming (Port Address +1) Offset 1 controls the paging bits for the ROM. This feature is needed for program- ming flash. Table 2- 13. Offset 1 Page Register for Programming (Port Address +1) Signal Result Control ROM/RAM15...
Chapter 2 – Installation · LPT1/COM2 RS-232 connector The BIOS setup determines whether the COM2 is used for the RS-232 connector or the IR interface. Jumpers on the touchscreen controller select the COM2 port or the auxiliary port. If a touchscreen controller is jumpered for COM2, this COM port is not available.
AHIP6+ Manual FPGA Program Connector (J15) This eight-pin connector is used to program the lattice FPGA. This pinout matches the standard lattice pinout. ISA/IDE Backplane Connector (ATIDE1) The ISA/IDE Backplane connector is a 120-pin connector. This connector provides both ISA and IDE signals to the backplane. IDE Connector (HDD1) IDE hard drive connector is a 40-pin header.
Chapter 3 – BIOS Setup Menus board’s The AHIP6+ customized BIOS has been designed to surpass the functionality provided for normal PC/ATs. This custom BIOS allows you to access the value-added features on the AHIP6+ module without inter- facing to the hardware directly. Moving through the Menus General instructions for navigating through the screens are described below: Result...
If the setup prompt is enabled on your sys- tem, the BIOS will display the following message: “Press F2 to enter Setup.” Xycom BIOS Setup Utility Main Advanced Security...
Cache RAM Displays the amount of cache detected and allows entry into the cache submenu. Shadow RAM Enables or disables the Shadow RAM access. IDE Submenu Xycom BIOS Setup Utility Main IDE Primary Master (C: 1082 Mb) Item Specific Help Type:...
2 = Editable only when Type is “User” 3 = Not visible when Type is set to “None” 4 = Not editable when Type is set to “Auto” Cache Submenu Xycom BIOS Setup Utility Main Memory Cache Item Specific Help...
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BIOS or AT-bus memory. Enabling cache may increase system performance, depending on how the extended BIOS is accessed. The default is disabled. Shadow RAM Submenu Xycom BIOS Setup Utility Main Item Specific Help Shadow RAM [384 KB]* Disabled – This block is not shadowed.
AHIP6+ Manual Advanced Menu Xycom BIOS Setup Utility Main Advanced Security Exit Item Specific Help ?I/O Device Configuration ?Advanced Chipset Control ?PCI Configuration If the item you are viewing has specific Installed O/S: [other] help, it will Reset Configuration Data: [No] be listed here.
Chapter 3 – BIOS Setup Menus I/O Device Configuration Submenu Xycom BIOS Setup Utility Advanced I/O Device Configuration Item Specific Help COM A: [Auto] * Base I/O Address [3F8] If the item you * Interrupt [IRQ4] are viewing has specific help, it will...
AHIP6+ Manual Advanced Chipset Control Submenu Xycom BIOS Setup Utility Advanced Advanced Chipset Control Item Specific Help Enable Memory Gap [Disabled] If the item you ECC Config: [Disabled] are viewing has SERR Signal Condition: [Multiple bit] specific help, it will 8-bit I/O Recovery: [3.5]...
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Chapter 3 – BIOS Setup Menus PCI Configuration Submenu Xycom BIOS Setup Utility Advanced PCI Configuration Item Specific Help ?PCI Device, Slot #1 If the item you ?PCI Device, Slot #2 are viewing has ?PCI/PNP ISA UMB Region Exclusion specific help, it ?PCI/PNP ISA IRQ Resource Exclusion will be listed here.
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Setup Defaults ¬® Select Menu Exit Enter Select » Submenu F10 Save & Exit PCI Device, Slot #2 Submenu Xycom BIOS Setup Utility Advanced PCI Configuration, Slot #2 Item Specific Help Option ROM Scan [Enabled] If the item you are viewing has...
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Chapter 3 – BIOS Setup Menus PCI/PNP ISA UMB Region Exclusion Submenu Xycom BIOS Setup Utility Advanced PCI/PNP ISA UMB Region Exclusion Item Specific Help CC00-CFFF [Available] If the item you are viewing has D000-D3FF [Available] specific help, it will be listed here.
Change Values Setup Defaults ¬® Select Menu Exit Enter Select » Submenu F10 Save & Exit On-board Socket Site Submenu Xycom BIOS Setup Utility Advanced On-board Socket Site Item Specific Help 32-pin Socket Site Address [Disabled] If the item you...
Chapter 3 – BIOS Setup Menus Flat Panel Submenu Xycom BIOS Setup Utility Advanced Flat Panel Item Specific Help Default Panel Type 640 x 480 STN If the item you Video Screen Expansion [ON] are viewing has Simultaneous Video [Disabled] specific help, it will be listed here.
AHIP6+ Manual Security Menu PhoenixBIOS Setup–Copyright 1985-95 Phoenix Technologies Ltd. Main Advanced Security Power Exit Item Specific Help Supervisor Password is: Clear User Password is: Clear Set Supervisor Password: [Enter] If the item you Set User Password: [Enter] are viewing has specific help, it will Password on boot: [Disabled]...
Chapter 3 – BIOS Setup Menus Option Description Diskette Access Restricts access to floppy drives to the supervisor when set to “Supervisor.” Requires setting the Supervisor password. User Mode Defines “User” access as [Normal] or [Restricted]. In normal mode you can access the data/time, user password, power, 32-pin socket, flat panel, boot order, and disk setup settings.
AHIP6+ Manual Device Monitoring Submenu Xycom BIOS Setup Utility Power Device Monitoring Item Specific Help IDE Primary Master [Disabled] If the item you IDE Primary Slave [Disabled] are viewing has IDE Secondary Master [Disabled] specific help, it will IDE Secondary Slave [Disabled] be listed here.
Chapter 3 – BIOS Setup Menus Boot PhoenixBIOS Setup–Copyright 1985-95 Phoenix Technologies Ltd. Boot Item Specific Help +Removable Devices +Hard Drive If the item you ATAPI CD-ROM Drive are viewing has Network Boot specific help, it will be listed here. ¯...
AHIP6+ Manual Exit Menu PhoenixBIOS Setup–Copyright 1985-95 Phoenix Technologies Ltd. Main Advanced Security Power Exit Item Specific Help Exit Saving Changes Exit Discarding Changes If the item you Load Setup Defaults are viewing has Discard Changes specific help, it will Save Changes be listed here.
Appendix B– Video Modes Introduction Appendix B defines the video modes and the panels the AHIP6+ supports. Video Modes The Chips & Technologies 69000 VGA controller supports many standard, VESA, and extended modes. The following tables list the standard and extended video modes and whether they passed, failed or are not supported with the CRT, TFT active color, or STN passive color displays.
Appendix B – Video Modes Windows 3.1 Windows 3.1 driver (version 1.1.8) C&T 69000 1024x768x16 1024x768x256 1024x768x32K 1024x768x64K 1280x1024x16 1280x1024x256 640x480x16 640x480x256 640x480x32k 640x480x64k 640x480x16M 800x600x16 800x600x256 800x600x32k 800x600x64k 800x600x16M = All windows' drivers were tested on a NEC multisync 5FG monitor...
Appendix C– Pinouts This appendix describes the pinouts for the AHIP6+ connectors defined in Chapter 2. VGA Connector (VGA1) Signal GREEN BLUE ORB_GND ORB_GND ORB_GND ORB_GND Fused VCC ORB_GND DDCDAT HSYNC VSYNC DDCCLK NC = no connect...
AHIP6+ Manual COM1 Connector RS-232/RS-485 (COM1_4) Signal Siganl DCD1 TXD- RXD1 TXD+ TXD1 TXD TERM - DTR1 TXD TERM + DSR1 RXD- RTS1 RXD+ CTS1 RXD TERM + RXD TERM - Note ‘A’ denotes the lower connector (RS-232) and ‘B’ denotes the upper connector (RS-485).
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Appendix C – Pinouts Signal Signal INIT SELIN DTR2 Note ‘A’ denotes the lower connector (LPT1) and ‘B’ denotes the upper con- nector (COM2, RS-232). This connector also contains the remote system reset option The reset jumper (J1) must be in position B for this option to work.
AHIP6+ Manual FPGA Program Connector (J15) Signal SDO* SDI* ISPEN* MODE* SCLK* DCIN1 Power Connector (PWR1) Signal Note -5V is not provided by the power supplies and will have to be created on the backplane board.
Appendix C – Pinouts Touch Control Connector (TCTRL1) Signal Signal KB_AIN0 +12V KB_AIN1 -12V RESET TXD2 TCH_RXD2 KB_P14 KB_P15 KB_P16 AUX_DATA KB_P17 AUX_CLK SENSE TCH_LED*...
Appendix C – Pinouts Internal Keyboard Connector (KYBD1) Signal KB_CLK KB_DATA 5VFUSE SPEAKER PS/2 Keyboard/Mouse Connector (KBMS1) Note If the touchscreen controller is using the mouse port, this interface will not be available. Signal Signal KB_DATA AUX_DATA 5VFUSE 5VFUSE KB_CLK AUX_CLK Internal Floppy Connector (FDD1) Signal...