Table of Contents
Advertisement
1.1
INTRODUCTION
CHAPTER 1
GENERAL INFORMATION
Monoboard Microcomputer
1 (Micromodu le
1),
as shown
in Figure
1-1
,
is a
complete compute r-on
-
a-board which will provide the O
EM
with a
solution
to
most
of
his processing
and con tro
l
applications.
This
module,
one of
a fami
ly
of
Micromodules,
conlains
Ihe
Microprocessor, the program
EROM
or
ROM
memory,
RAM
memory,
programmable input/oulput
interfaces, and
Ihe
required clock,
restart,
bus
inler-
face,
and
control
circuitry.
All
address
references within
this
manual
are shown
in hexadec-
imal
unless
otherwise
indicated
.
1.2
FEATURES
The features
of
Monoboard
Microcomputer
1
include:
•
MC6800
Microprocessing
Unit
(MPU) with its associated clock
oscillator,
power on
reset timer
,
and
memory
decoding
logic.
•
1024
bytes
of
Random
Access Memory (RAM)
.
•
Sockets
for up
10
4096
bytes
of Erasable
Read
Only
Memory (EROM)
or
mask
programmable
Read
Only
Memory
(ROM).
•
Three prog rammable Peripheral Interface Adapter (PIA)
devices
providing
60
programmable
Input/Output and control
lines.
•
Address
, data,
and control
bus drivers
to interface
Monoboard
Microcomputer
1
wilh other
modules in the family
or with
the
EXORciser.
•
TTL
signal
level inputs
and
TTL
signal teve
l,
three
state,
or open
collector
outputs.
•
Oplional
maling connectors,
and pullup
resistors
for PIA
oulput lines
(available on
M68MMO
H and
M68MM0 1-2
only. See schemalic
and
parts
list.)
1.3
SPECIFICATIONS
Monoboard Microcomputer 1
speci fications are identi fied in
T
able 1-1.
1.4 GENERAL DESCRIPTION
Th
e
Monoboard Microcomputer
1
provides the user with
all
of
the
processing
and control power of an
MC6800 Microprocessing Unit
(MPU) working wit
h 1 K
of
RAM
,
up
10
4K of
EROM
or
ROM
for
pro gramming
,
and three
programmable
Peripheral
Interface
Adapters
(PI
A)
. Additionally,
the
user
has the
op
ti
on
of
interfacing
Monoboard Microcomputer 1
(via its
address, data,
and
control
bu
s
buffers)
wi
th other
modules
in
the Micromodule family
and with
the
EXORciser.
T
he
board
also contains
th
e
required two-phase
clock
generator,
th
e
reset
tim er
for
power
turn-on initialization
,
add ress
bus decoding for
establishing
the
add resses
for each
part,
and
th
e
refresh
circuit for
use
with optional
external
dynamic
memories.
T
he
PIA's
input/output
sig nals
are identified
in Table
1-
1.
1-1
Advertisement
Table of Contents
