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3.3 Descriptions on signal functions
3.3.1 PCI bus
PCI bus of SCE8720C complies with the PCI2.1..
Signal name
(57 pins in total)
AD[31:0]
CBE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
LOCK#
SERR#
PERR#
RST#
REQ[1:0]#
GNT[1:0]#
PCLK[2:0]
INT[A,B,C,D]#
Rev.A
I/O
I/O
Address and data bus signals. Transfers addresses
and data by time division.
I/O
Bus command and byte enable. Transfers by time
division.
I/O
parity data of 36-bit of AD[31:0] and CBE[3:0]#.
S/T/S
Signal indicating the cycle frame.
S/T/S
Ready signal of the initiator.
S/T/S
Ready signal of the target.
S/T/S
Signal
from
canceleration.
S/T/S
Signal from the PCI slave indicating that it is selected.
S/T/S
Signal used when exclusively accessing the target.
I/OD
Signal indicating that a fatal error has occurred.
S/T/S
Parity error signal.
O
PCI reset signal.
I
Bus request signal.
O
Permission signal to use bus.
O
PCI clock
I
PCI interrupt signal.
EPSON
CARD-PCI/GX Hardware Manual
Function description
target
requesting
transaction
27
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