Ic Block Diagram (Ic :F Circuit Boards (:.T-Test Program Ainspections (~~) - Yamaha Clavinova CVP-96 Service Manual

• HD63266F (Xl939A00) FDC (Floppy Disk Controller)
PINN NAME
1/0
FUNCTION
PIN
NAME
o.
NO.
1 8"//5" I Data transmission speed 33 /TAKO
2 XTALSET I Clock select 34 /INDEX
3 /RESET I Rest 35 /RDATA
4
E//RD
I Enable/Read 36 XTAL2
5 RW//WR I Read/write/Write
37 EXTAL2
6 /CS I Chip select 38 NC
7 /DACK I DMA acknowledge 39' XTAL1
8 RS0 I Register select 40 EXTAU
9 RS1 I 41 VSS4
10
VSS1
J
Ground 42 VSS5
11 VSS2
43
NC
12 DO 1/0 44 VCC2
13 D1 1/0 45 VCC3
14 D2 1/0 46 VCC4
15 D3
1/0
Data bus 47 /WGATE
16 D4
l/0
48 NJDATA
17 D5 1/0,
49 ·
VSS6
18 D6 1/0 50 /STEP
19 D7 1/0 51 /HDIR
20 /DREQ 0 DMA request 52 /HLOAD
21 /IRQ 0 Interrupt request 53 /HSEL
22 /DENO I Data end 54 · VSS7
23
VSS3 Ground 55 /DS0
24
1/2 EX1 56 /DS1
. 25 VCC1 Power supply 57
/DS2
26
NUM1
I
58 /DS3
27 NUM3 I
59
vss8
28 IFS I Host interface select 60 /MONO
29 SFORM I Format data 61 /MON1
30 /INP I Index pulse 62 /MON2
31 /READY I Ready from FDD 63 /MON3
32 /WPRT I Write control signal 64 VSS9
• LC7886M (XO007 A00) ADC (Analog to Digital Converter}
PIN
NAME 1/0 FUNCTION
P·IN
NAME
NO. NO.
1 ADIN1 I CH1 analog input 13 DGND
2 VH Reference voltage "H" 14 TSTOUT
3
AVDD Analog power supply 15 TEST1
4 VR1 CH1 (VH+VL)/2 Reference voltage 16 TEST2
5 TEST3 Test pin (Connected to analog GND) 17 TEST4
6 AVDD Analog power supply 18 TEST6
7 FORM l When FORM="H", 19 AGNO
LRCK="L":CH1, LRCK="H":CH2
When FORM="L",
LRCK="H":CH1, LRCK="L":CH2
8 IFDA I "H":18 bit digital data, 20 TEST5
"L":16 bit digital data
9
LRCK l CH1/CH2 select 21 VR2
10 BCLK I Bit clock
22
VL
11 ADDATA
0
Data output
23 AOIN2
12 DVDD Digital power supply
24
AGND
CVP~96/CVP-98
1/0
FUNCTION
I Track 00 signal
I Index signal
I Read data input from FDD
J
Clock
J
Clock
j Ground
}
Power supply
0 Write control
0 Writ data to FDD
Ground
0 Step signal to control head of FDD
0 Direction
0 Head load
0 Head select
Ground
0
I
0 Drive select
0
0
Ground
0 l
0 Motor on
0
0
Ground
1/0 FUNCTION
DigitalGND
I
I
I Test pin (Connected to digital GND)
I
I
AnalogGND
Test pin (Connected to analog GND)
CH2 (VH+VL)/2 Reference voltage
Reference voltage "L"
I
CH2 Analog input
AnalogGND
44
CVP-96/CVP-98
• PCM1702U (XP551A00) DAC (Digital to Analog Con~erter)
PINN
NAME 1/0 FUNCTION
PIN
I NAME
o.
NO.
1 DATA I Data input 11
I
+VCC
2 CLK I Clock
12
BPO
3 NC
13 NC
4 +VDD
Power supply (+5 V) 14 IOUT
5
D.GND Digital ground 15 A.GND
6 -VDD Power supply (-5 V) 16 A.GND
7 L.E I Latch enable 17 SERV
8 NC
18 NC
9 NC
19
i
REF
10
NC
20
!
-VCC
■
IC BLOCK DIAGRAM {IC
7·
□
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• TC74HC00AF-TP1 (XD655AOO) • SN74HC04N (IG142250)
Quad 2 lnputNAND • TC74HCU04AF-TP1 (XD660AOO)
• TC4069UBF-T1 (XE054AOO)
Hex Inverter
1/0 FUNCTION
Power supply (+5 V)
Bipolar de-couple
0 Output current
Analog ground
Analog ground
Servo de
0
couple
Reference de-couple
Power supply (-5
V)
• HD74AC32FPER (XK452AOO)
Quad 2 Input OR
• SN74HC132NS-R (XL 112AOO) • HD74LVC139FP (XS048AOO) • µPC4570HA (XB247AOO)
Quad 2 Input NAND Schmitt Trggers • SN74HC139NSR (XS127 AOO)
Dual Operational Amplifier
Dual 2 to 4 Demultiplexer .
+V
+IN OUT
B B B
45
-D<
•L
C
DM
PNL
PNF
MV
ENC
PNC
PNC
PNC
EQ
JAC
MIC
HP