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5. DIAGNOSIS

5.1 POWER ON SEQUENCE

A
MAIN MICROCOMPUTER
Power ON
Interrupt inhibit
Mute ON
B
Port initial setting
(port mode register setting),
each IC reset signal output)
T-USB reset
Sub microcomputer reset
C
FPGA reset
DSP reset
DAC, ADC, DIR reset
D
Waiting for countermeasure
of the relay chattering
Cancel T-USB reset
Start a clock supply to
the sub microcomputer
E
Sub microcomputer
clock stability wait
Cancel the reset of the sub
microcomputer.
Note: The DPRAM access is impossible.
Sub microcomputer
initialization wait
F
Initial setting of
the main computer
18
1
2
Pin 69 of IC1007 turns
Mute ON at H.
Pin 29 of IC1007 resets
T-USB at L.
Pin 73 of IC1007 resets
sub microcomputer at H.
Pin 85 of IC1007 resets
FPGA at L.
Pin 79 of IC1007 resets
DSP at L.
Pin 81 of IC1007 resets
DAC at L.
Wait time: 100 msec
Pin 29 of IC1007 cancels
T-USB reset at H.
Wait time: 10 msec
Pin 73 of IC1007 cancels
sub microcomputer reset at H.
Wait time: 10 msec
DJM-5000
2
3
Pin 79 of IC1007 resets
Cancel DSP reset
DSP at H.
FPGA program load
Waiting for DSP stability
Wait time: 100 msec
Pin 85 of IC1007 cancels
Cancel FPGA reset
FPGA reset at H.
Waiting for FPGA stability
Wait time: 100 ms
DPRAM (@FPGA)
check
Sub microcomputer
Pin 74 of IC1007 enables
DPRAM access enabled
DPRAM access at H.
Waiting for sub
Wait time: 10 msec
microcomputer stability
Handshake with the
sub microcomputer
Send mute command to
the sub microcomputer
Pin 81 of IC1007 resets
Cancel DAC and DIR reset
DAC at H.
Waiting for DAC stability
Wait time: 100 msec
Pin 77 of IC1007 is DAC
Initial setting of
select at H, and pins 76 and
the MASTER DAC
78 are data and clock.
Handshake with the DSP
DIR initial setting
3
4
4

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