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SE LECTED DATA
REGISTER CIRCUIT
leered data} of Dala
~
s $1202 thru 51205
V
3)
is entered
into
r--~~~~----B>-~~~---"--r-")
i~a~c:'u~::~7fOW~~~
U121B 1 )c"'---;:>-~~~--!!l1l!.
osition.
The/arched
n on
the
MUXbus
vnen U1210B·6 goes
01
10
Ul211C
lO''--t>-~~~~
12
+5V
R1218
47K
09~"-~-t>-~___,
RESS COMPARATOR CIRCUIT
09C;'JC>,,,,0~--£;>---l
13
U12110
»"-'-'-t>-~~~_~~
J
4-81T
LATCH SO
4- LINE - TO -16- LINE
DECODER
SA
A~
8¢
11
81
SAl
3
10
Al
82
83
BA2
21
A2
84
85
BA3
22
A3
86
87
8B
IB
Qi3r--+----------------------------------------+------------
Qll--"-~__j)>-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-+-------------,
Q2
11
Q3
14
QOfL-__j)>-----------------------------------------------,
Ql!--!--__j)>--------------~-----------------------___,
02 10
Q3
15
[}
LED 5-VOLT
SWITCHES
(Q1201-QI204)
R1222
U1203
O¢
01
12
02
13
03
S
9
ClK
ClR
When .wltch
S1211 Ja actuated
to TEST position,
MUXbu'
~
Dat.
Display
Latch U1203 forces
811 LED 5-voft swItches
(01201 thru Q12CU) on, lind causes
thct auxiliary
(DS1210)
and o".,atlng
(DS1209) channel displays to Indlc,t.
$F.
SimultaneouSly,
4-blt 'slch
& 4·Lln8-fo-16-Llne
Decod.,
U120f
fePHt&dly
ripples
through
the LED ground swit-
ch •• (01205 th,u QI220).
Theso two actfons
ceuse all 64
0
LED's of the station
parameter
status
display
matrix
(D51201 thru 051208) to light.
R1223
82
Rt224
82
R1225
82
Q1202
M9649
Q1203
M9649
Q1201
M9649
RI221
R1219
RI220
2K
2K
2K
2K
o
U1203 Decodes and latches
MUXbus data lines
R1253
13K
R1255
13K
Q1207
M9706
R1256
13K
R1258
13K
Q1210
M9706
R1259
13K
R1260
13K
LED
GROUND
SWITCHES
(Q1205 - Q1220)
17
015
R1261
13K
R1263
13K
Q1215
M9706
Provides pulse to latch AWXbus Addrfflss end Data Into
U1201sndU1203.
R1264
13K
R1266
R1267
Latches and
decodes MUXbus
address lines
13K
Q1218
M9706
13K
R1268
13K
STATION
PARAMETER
STATUS
DI SPLAY
MATRIX
89
Q1204
M9649
4
+5V
RI289
47K
88
R1226
82
10 9
6
5
03 02 0\ O¢
UI204
PfO
J120!
17
' " J
18
SOl
¢
IAUXbu.
O.t.•
19
'802
Un.!
20
803
ABCOEFG
12 13 14 15 1
2
3
10985423
ABCoEFG
~_A~_
COM
DS12iO
AUXILIARY
CHANNEL
DISPLAY
+5V
U1201
RI212
89
17
47K
810
20
When HI, all
outputs low
0
23
811
19
INHIBIT
U1206A
14
3
CD
7
I
13
Q
813
U1202A
1-
814
16
STROBE
15
+ 5V
CR120!
R1290
13K
CLOCK
PULSE
C1240
.01
I
I
89
.,
12
I
U1206E
11
89
Clock Pulse generating
Circuit used to latch aux
iliary
channel
number
data
into
U1204,
See
Channel Display
Timing
Diagram
R1288
47K
R12B7
47K
R1286
4':"K
6 5
ABC'
0
E
F
G
12 13 \4 15 1
2
3
03 C2 01
o¢
U1205
COM
+ 5V
CR1202
I
!
R1291
13K
CLOCK
PULSE
C1241
.01
88
10
U1206D
J
88
LEGEND:
THEORY
NOTE
LOGIC GND
---&>--
CONTROL
SIGNAL
BCD-TO-
HEX
7-SEGMENT
LATCH-DECODER -
DRIVER
CHANNEL DISPLAY
TIMING
DIAGRAM
I I
S80RS9~
-
-
I
SB OR 89
LLs--
ClOCK~~.
PULSE'
V!
I
!
I'
I
LOAD
LATCH
DS1209
DATA
DATA
OPERATING
CHANNEL
DISPLAY
UNUSED
CIRCUITS
~
"
U12068
7"' - -.6
~
Clock Pulse generating
circuitu,sed
to latch operating
Channel number
data into U1205, See Channel Display
Timing Diagram
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