GE 235 System Manual page 34

P Counter
The P counter is a 15-bit sequence control counter that contains the memory address of the next
instruction to be executed. The contents of the P counter a r e incremented by one after the current
instruction has been selected from memory and placed in the I register, s o that the
P
counter
normally indicates the address of the next instruction in sequence. The contents of the P counter
can be s e t from the I register during the execution of branching instructions specified by the pro-
gram.
M Register
The M register is a 21-bit register that a c t s a s an input-output buffer between the magnetic core
memory and the Central P r o c e s s o r o r peripheral equipment. When a word enters the M register
from the Central Processor o r punched card equipment for recording in memory, a parity bit
is
computed and 21 bits a r e storedin memory. Peripheral controllers that a r e connected through the
numbered priority control channels generate a parity bit which is checked in the M register p r i o r
to the storage of the 21-bit word in memory. When a word is read from memory into the M
register, parity
is
again computed and the new parity bit i s compared with the one already existing
to ensure accuracy of data transfers.
Adder
The adder of the Central P r o c e s s o r i s a high-speed, parallel, binary adder network that executes
the calculations specified by the instruction code in the I register during arithmetic operations.
Real Time Clock
The Clock, o r C register, is a 19-bit register (there i s no sign bit). While power i s applied to the
Central Processor, the C register i s automatically incremented by a binary one every sixth of a
second. When the count reaches 518,400, the decimal equivalent of 24 hours in sixths of a second,
the C register
is
automatically reset on the next increment to all zeros and s t a r t s counting again.
The real time clockis loadedfrom the A register, and i t s contents can be read by transferring them
to the A register. The clock can be s e t o r read either by program o r by manually inserted instruc-
tions.
AUXILIARY ARITHMETIC UNIT
The addition of the GE-235Auxiliary Arithmeticunit (AAU) extends the arithmetic capability of the
GE-235 system. This device, with built-in logic, facilitates floating point and double precision
arithmetic through i t s increased capacity and the speed with which i t computes. The Auxiliary
Arithmetic Unit contains two 40-bit registers, AX and QX, which correspond functionally to the A
and Q registers in the Central Processor. Eighty bits permit the unit to add, subtract, multiply
and divide extremely large numbers represented in either fixed o r floating point format. At the
option of the programmer, the unit functions in three modes: normalized floating point, unnormal-
ized floating point, and fixed point computations. Underflow and overflow conditions a r e checked
by means of programmed interrogation.