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17.5
Operation
The PS/2 interface module supports some registers and hardware circuit to implement standard
PS/2 interface. At the following sections, they describe the serial data format, software operational
sequence and communication protocol. These descriptions take the keyboard operation as principal
thing.
17.5.1
Serial Data Format
The keyboard's serial data format is shown in Figure 17-2. Serial data is asynchronous and consists
of 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit. The data-stream order is LSB first. The parity
bit is added after the data stream, so that eight data bits and the parity bit always have an odd
number of 1s.
Start
bit
17.5.2
Software Operational Sequence
Receiving Data from the Keyboard
1. Set the KBCIE bit of KBCSR to 1, and clear the KBCOE/KBDOE bit to 0. This enables the
system to receive data from the keyboard (when KBCK input is enabled, the signal output
buffer is disabled.)
Example: Set H'8000 to KBCSR.
2. When data is received, an interrupt is set and the scan code of the key is placed in the lower
nine bits of KBCSR, including the parity bit. Check the received data full flag (KBRDF, bit 0
of KBISR); it indicates the cause of an interrupt (the flag checks the bit count).
3. Check the parity bit before data processing. The parity bit is indicated by bit 8 of KBCSR. The
parity bit indicates an odd parity. If parity is abnormal, software must send the re-send
command (H'FE) to the keyboard.
4. After data reception, hardware stops incoming data by driving KBCK signal to low. The
KBCIE bit is cleared to 0 automatically.
5. To enter the data reception waiting state, the KBCIE bit must be set again. To clear the cause of
the interrupt, software must clear the KBRDF bit.
D0
D1
D2
Figure 17.2 Keyboard Serial Data Format
D3
D4
D5
Parity
D6
D7
bit
Rev. 3.0, 03/01, page 255 of 390
Stop
bit
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