Samsung S3F84B8 User Manual page 11

Figure
Number
Figure 1-1 S3F84B8 Block Diagram .................................................................................................................. 1-5
Figure 1-2 S3F84B8 Pin Assignment (20-DIP, 20-SOP) ................................................................................... 1-6
Figure 1-3 Pin Circuit Type 1 ............................................................................................................................. 1-9
Figure 1-4 Pin Circuit Type 2 ............................................................................................................................. 1-9
Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)........................................................................ 1-10
Figure 1-6 Pin Circuit Type 1-2 (P2.3) ............................................................................................................. 1-11
Figure 1-7 Pin Circuit Type 1-3 (P0.3, P0.4, P0.6) .......................................................................................... 1-12
Figure 1-8 Pin Circuit Type 2-1 (P0.5) ............................................................................................................. 1-12
Figure 1-9 Pin Circuit Type 3 (P0.2)................................................................................................................. 1-13
Figure 1-10 Pin Circuit Type 2-2 (P0.0, P0.1) .................................................................................................. 1-13
Figure 2-1 Program Memory Address Space..................................................................................................... 2-2
Figure 2-2 Smart Option..................................................................................................................................... 2-3
Figure 2-3 Internal Register File Organization in S3F84B8 ............................................................................... 2-5
Figure 2-4 Register Page Pointer (PP) .............................................................................................................. 2-6
Figure 2-5 Set 1, Set 2, Prime Area Register Map ............................................................................................ 2-8
Figure 2-6 8 Byte Working Register Areas (Slices) ........................................................................................... 2-9
Figure 2-7 Contiguous 16 Byte Working Register Block.................................................................................. 2-10
Figure 2-8 Non-Contiguous 16 Byte Working Register Block .......................................................................... 2-11
Figure 2-9 16-Bit Register Pair......................................................................................................................... 2-12
Figure 2-10 Register File Addressing............................................................................................................... 2-13
Figure 2-11 Common Working Register Area .................................................................................................. 2-14
Figure 2-12 4-Bit Working Register Addressing............................................................................................... 2-15
Figure 2-13 4-Bit Working Register Addressing Example................................................................................ 2-16
Figure 2-14 8-Bit Working Register Addressing............................................................................................... 2-17
Figure 2-15 8-Bit Working Register Addressing Example................................................................................ 2-18
Figure 2-16 Stack Operations .......................................................................................................................... 2-19
Figure 3-1 Register Addressing ......................................................................................................................... 3-2
Figure 3-2 Working Register Addressing ........................................................................................................... 3-2
Indirect Register Addressing to Register File ................................................................................... 3-3
Figure 3-3
Figure 3-4 Indirect Register Addressing to Program Memory............................................................................ 3-4
Figure 3-5 Indirect Working Register Addressing to Register File ..................................................................... 3-5
Figure 3-6 Indirect Working Register Addressing to Program or Data Memory ................................................ 3-6
Figure 3-7 Indexed Addressing to Register File................................................................................................. 3-7
Figure 3-8 Indexed Addressing to Program or Data Memory with Short Offset ................................................ 3-8
Figure 3-9 Indexed Addressing to Program or Data Memory ............................................................................ 3-9
Figure 3-10 Direct Addressing for Load Instructions........................................................................................ 3-10
Figure 3-11 Direct Addressing for Call and Jump Instructions......................................................................... 3-11
Figure 3-12 Indirect Addressing ....................................................................................................................... 3-12
Figure 3-13 Relative Addressing...................................................................................................................... 3-13
Figure 3-14 Immediate Addressing .................................................................................................................. 3-14
Figure 4-1 Register Description Format ............................................................................................................. 4-4
List of Figures
Title Page
Number