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PZ-43MR2E
PZ-50MR2E
PC I/F BLOCK DIAGRAM
CPCI-00 56CE
H
12
CLR_ SW
7
9
10
5
1
G
3
18
17
F
29,3
0
25,2
6
21,2
2
E
ACL_S IG
D
13,1
4
9,10
5,6
RT, RB SETTING
2
C
1
B
A
1
2
PC _H
1B
P C_V
2B
P C_C
4B
V0
Sync
Sel
1A
2A
IC411
MAIN _H
74LCX157
4A
D
MAIN_VD
HV SEL
-A /+B
P C_R
12V->5VReg
PC _G
IC7 PQ0 5TZ11
P C_B
RIN2
GIN2
BIN2
MAI N_
RIN1
R
MAI N_
GIN1
G
MAI N_
BIN1
B
12V->9V R eg
IC415 B A09FP
CXA3506R
ROUT
2
I
VIDEO SIGNAL
GOUT
PEAK DETECTION
BOUT
OV0_CLP
5V->3.3V Reg
IC8 PQ2 0VZ11
SUB _Y
AIN
SUB_ Cb
BIN
V1
A/D
SUB_ Cr
CIN
IC310
V1 ADC
3.27V
RT
TLC57 33A
1.17V
RB
CIRCUIT
V1
PLL
About 60MHz
VCOOUT
IC328
TLC 2933IPW
3
4
X4
25MHz
1Y
OV0 _H
2Y
OV0_V
4Y
PC_ C3
CXA3506R
OV0_PDEN
VCO
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
SYNCIN1
SYNCIN2
HOLD
OV0_CLP
CLPIN
V0
OV0_HSC2
DIVOUT
A/D
OVCLK(Max60MHz)
1/2C LK
Amp
8
PLL
RA[7..0]
8
RB[7..0]
IC4
8
GA[7..0]
8
GB[7..0]
C=CH2
8
BA[7..0]
8
BB[7. .0]
XPOWERSAVE
XPW R_SV
AO[8..1]
BO[8..1]
CO[8..1]
OV1_VCKO
CLK
(≒ 15M Hz)
OV1_CLP
EXTCLP
- OE
SAD C_OE
OV1_HSNR
FIN-A
OV1_HSNF
FIN-B
OV1_PDEN
PFDINH
OV1 _H
OV1_V
OV1_VCLK
5
6
7
60
MCK_REF
DCLK
V0_HSYNC
DO_RA[9.. 2 ]
V0_VSYNC
DO_GA[9.. 2 ]
V0_CSYNC
DO_BA[9..2]
LCLK
DO_HSYNC
V0_PDEN
DO_VSYNC
DO_HDISP
V0_HSYNR
V0_CLP
V0_HSYNC2
V0_VDCLK_I
V0_RA[7..0]
V0_RB[7..0]
BINT
CVIC
V0_GA[7.. 0 ]
V0_GB[7..0]
V0_BA[7..0]
IC25
V0_BB[7..0]
8
V1_GA[7.. 0 ]
8
V1_BA[7..0]
BCLK
8
V1_RA[7..0]
XBCS
V1_VDCLK_O
BWAIT
V1_CLP
XRESET
PLL_S
V1_HSYNR
V1_HSYNF
BD,BA
V1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
SDRAM
512Kx128bitx4 BANK
IC319-322
HY57V653220BTC-7 4 PCS.
8
9
X6
25.175MHz
X5
79.794MHz
8
8
8
LCLK(79.79 4MHz
DO_HS YNC
DO_VS YNC
DO_HD ISP
-C1_I NT
TXD
RXD
TXD
RXD
CKIO(24MHz)
-CS2
-WAIT _C1
-RESET_C1
-
RST_P LL
CPU BUS D
F
F
WP
2M
LH28
DR
MS
E
AT
I
10
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