Gpc5/6/7 Pin Configuration Table In Irom Boot Mode; Nand Flash Memory Timing - Samsung S3C2416 User Manual

S3C2416 RISC MICROPROCESSOR

5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE

MMC(MoviNAND/iNand)
Reserved
Nand
Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode. If NAND
Flash is not used as boot memory, the configuration can be changed by setting NFCON SFR 'NFCONF'
(0x4E000000). PageSize, PageSize_Ext and AddrCycle are fields in NFCONF(0x4E000000).

6 NAND FLASH MEMORY TIMING

HCLK
CLE / ALE
nWE
DATA
Figure 7-3. CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram
Page Address Cycle
- -
- -
3
512
4
4
2048
5
4096 5
TACLS
COMMAND / ADDRESS
GPC7 [2]
0
0
0
0
1
1
1
TWRPH0 TWRPH1
NAND FLASH CONTROLLER
GPC6 [1] GPC5 [0]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
7-3