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16 ÷ 8-bit register-register divide:
16 × 16-bit register-register multiply:
32 ÷ 16-bit register-register divide:
• Two CPU operating modes
Normal mode*/Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Note: * Normal mode is not available for this LSI.
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Instruction
MULXU
MULXS
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on the product.
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers, and one 8-bit control register, have been added.
Rev. 1.0, 02/00, page 18 of 1141
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, Erd
MULXS.B Rs, Rd
MULXS.W Rs, Erd
1200 ns
2000 ns
2000 ns
Number of Execution States
H8S/2600
3
4
4
5
H8S/2000
12
20
13
21
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