Lsi Pin Description - Yamaha DISKLAVIER MX1Z Service Manual

MX1Z

LSI PIN DESCRIPTION

•M37700SAFP (XI286A00) CPU······················································································ 14
•HD63266F (XI939A00) FDC ··························································································· 15
•SCI (XS345A00) CPU ····································································································· 15
•LC92011B-656 (XK441A00) GATE ARRAY··································································· 16
•RF5GF26-028 (XK652A00) GATE ARRAY ···································································· 17
•YM3421-F (XL150A00) PWM GENERATOR ································································· 18
•HD6433258C02F (XQ462C00) CPU ·············································································· 18
•HD6417032-F20 (XQ958A00) CPU ················································································ 19
M37700SAFP (XI286A00) CPU
PIN
NAME I/O
NO.
1 ANO. P70 I Port 7, Analog input
2 P67 I/O
3 P66 I/O
4 P65 I/O
5 P64 I/O
Port 6
6 P63 I/O
7 P62 I/O
8 P61 I/O
9 P60 I/O
10 P57 I/O
11 P56 I/O
12 P55 I/O
13 P54 I/O
Port 5
14 P53 I/O
15 P52 I/O
16 P51 I/O
17 P50 I/O
18 P47 I/O
19 P46 I/O
20 P45 I/O
21 P44 I/O
22 P43 I/O
23 P42 I/O
24 /RDY. P41 I Ready
25 /HOLD. P40 I Hold request
26 BYTE I Byte enable
27 CNVSS I Processor mode control
28 /RES I Reset
29 XIN I Clock
30 XOUT O Clock
31 /E O Enable
32 VSS Ground
33 /HLDA. P33 O Hold acknowledge
34 ALE O Address latch enable
35 /BHE. P31 O Byte high enable
36 R/W O Read write control
37 D7 I/O
38 D6 I/O
Data bus
39 D5 I/O
40 D4 I/O
14
FUNCTION
PIN
NAME I/O
NO.
41 D3 I/O
42 D2 I/O
Data bus
43 D1 I/O
44 D0 I/O
45 A15 O
46 A14 O
47 A13 O
48 A12 O
49 A11 O
50 A10 O
51 A9 O
52 A8 O
Address bus
53 A7 O
54 A6 O
55 A5 O
56 A4 O
57 A3 O
58 A2 O
59 A1 O
60 A0 O
61 TXD1. P87 O Transfer data channel
62 RXD1.P86 I Receive data channel
63 P85 I/O Part 8
64 /CTS1./RTS1 I/O Clear to send channel 0/
Request to send channel 0
65 TXD0. P83 O Transfer data channel 0
66 RXD0.P82 I Receive data channel 0
67 P81 I/O Port 8
68 /CTS0./RTS0 I/O Clear to send channel 0/
Request to send channel 0
69 VSS Power supply
70 AVCC Analog power supply
71 VREF I Reference voltage
72 AVSS Analog ground
73 VSS Ground
74 P77 I/O
75 AN6.P76 I Port 7
76 AN5.P75 I
77 AN4.P74 I
78 AN3.P73 I Port 7 Analog input
79 AN2.P72 I
80 AN1.P71 I
PK-CTL: IC3
FUNCTION