Character Rom; Detailed Circuit Description; Gate Array Functional Description - Zenith Z-100 PC series Service Manual

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3.26
Circuit Description
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Character ROM
Data output of the RAMs is used to provide the character generator ROM
with a valid 8-bit address. The address selects a particular memory loca­
tion in ROM that contains data required to generate a character on the
display.
Detailed Circuit Description
• Character Addressing - Data placed on the VRAMO through VRAM7
bus by the video RAMs is latched by octal buffer U319 when the
ROMG* signal from pin 6 of the gate array is active-low. The latched
data byte provides the character generator ROM with a valid 8-bit
address value.
• Read Cycle -
When the ROM receives a valid address from video
RAM, the value represented is used to select a desired character from
the font. The data byte output from the ROM is latched onto the GAO
through GA7 data bus by flip-flop U328 during the time when the
ROMG* signal from pin 6 of the gate array goes high. The gate array
reads the data on the GAO through GA7 bus and then processes the
data internally.
Gate Array Functional Description
The video controller gate array is an active device responsible for manipu ­
lating and processing data to derive desired output signals. Gate array
technology provides an extremely flexible basis for many different internal
circuit configurations. Video synchronization and control, as well as multi­
plexing, decoding, and timing are all functions accomplished by the gate
array. Refer to Table 3.11 for gate array pinout and signal names. Refer
to Figure 3.4 for Gate Array Block Diagram.
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