Es3883 Video Cd Companion Chip; Pin Description - Philips FW-V720 Service Manual

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ES3883 VIDEO CD COMPANION CHIP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DSC_D7 81
HSYN_B
82
DSC_D6
83
VSYN_B
84
DSC_D5 85
YUV7 86
YUV6 87
YUV5 88
YUV4
89
VCC
90
VSS 91
YUV3 92
Companion Chip
DSC_D4 93
YUV2 94
DSC_D3 95
YUV1 96
DSC_D2 97
YUV0 98
DSC_D1 99
VSS 100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

PIN DESCRIPTION

Name Number I/O Definition
VSS 1,25:26,31,72,75,77,91,100 I
VCC 5,16,32,66,73,78,90 I
DSC_C 6 I
AUX0 7 I/O
AUX1 9 I/O
AUX2 11 I/O
AUX3 70 I/O
AUX4 69 I/O
AUX5 68 I/O
AUX6 67 I/O
AUX7 14 I/O
AUX8 18 I/O
AUX9 20 I/O
AUX10 34 I/O
AUX11 35 I/O
AUX12 36 I/O
AUX13 38 I/O
AUX14 39 I/O
AUX15 40 I/O
DSC_D[7:0] 81,83,85,93,95,97,99,8 I/O
DSC_S 10 I
DCLK O
12
EXT_CLK I
RESET_B 13 I
MUTE 15 O
MCLK 17 I
TWS I
19
SPLL_OUT O
8-5
51
50 MIC2
MIC1
49
AOL+
48
AOL-
47
AOR-
46
AOR+
45
Visba ES3883
44 VCCAA
43 VREFP
VCM
42
Video CD
VSSAA
41
AUX15/IR
40
39 AUX14/SOS1
38 AUX13/SP
37 RBCK/SER_IN
36 AUX12/C2PO
35 AUX11/IRQ
34 AUX10/SQCK
33 RSD/SEL_PLL0
32 VCC
31 VSS
30
Ground.
Voltage supply, 5 V.
Clock for programming to access internal registers.
Servo Forward or Control Pin.
Servo Reverse or Control Pin.
Servo LDON or Control Pin.
Servo CW/Limit or Control Pin.
Servo CCW/Close or Control Pin.
Servo Data or Control Pin.
Servo XLAT or Control Pin/VFD_DO.
Servo BRKM/Sense or Control Pin/VFD_DI.
Servo Mute/Open or Control Pin/VFD_CLK.
Servo SQS0 or Control Pin.
Servo SQCK or Control Pin.
3880 IRQ or Interrupt Output or Control Pin.
CD C2PO or Interrupt Input or Control Pin.
Serial Interrupt/CD-Mute or Control Pin.
Servo SCOR (S0S1) or Interrupt Input or Control Pin.
Interrupt Input or Control Pin.
Data for programming to access internal registers.
Strobe for programming to access internal registers.
Dual-purpose pin DCLK is the MPEG decoder clock.
EXT_CLK is the external clock EXT_CLK is an input during bypass PLL mode.
Video reset (active-low).
Audio mute.
Audio master clock.
Dual-purpose pin TWS is the transmit audio frame sync.
SPLL_OUT is the select PLL output.
Name Number
TSD 21
TBCK 22
RWS
SEL_PLL1
23
RSTOUT_B 24
NC 2:4,27:30,76
RSD
33
SEL_PLL0
RBCK
37
SER_IN
VSSAA 41,51
VCM
42
VREFP 43
VCCAA 44
AOR+, AOR- 45:46
AOL-, AOL+ 47:48
MIC1 49
MIC2 50
VREF
52
VREFM 53
RSET 54
COMP 55
VSSAV 56:57,62:63
CDAC 58
VCCAV 59,60
YDAC 61
VDAC 64
ACAP 65
XOUT 71
XIN 74
PCLK 79
2XPCLK 80
HSYN_B 82
VSYN_B 84
YUV[7:0] 86:89,92,94,96,98
Published in Heiloo, Holland.
8-5
I/O Definition
I Transmit audio data input.
I Transmit audio bit clock.
O Dual-purpose pin RWS is the receive audio frame sync.
I Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1 SEL_PLL0 DCLK
0 0 Bypass PLL (input mode)
0 1 27 MHz (output mode)
1 0 32.4 MHz (output mode)
1 1 40.5 MHz (output mode)
O Reset output (active-low).
No connect. Do not connect to these pins.
O Dual-purpose pin. RSD is the receive audio data input.
I SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output. See the
table for pin number 23.
O Dual-purpose pin. RBCK is the receive audio bit clock.
I SER_IN is the serial input DSC mode.
0 - Parallel DSC mode.
1 - Serial DSC mode.
I Audio Analog Ground.
I ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V. Bypass to
analog ground with 47 m F electrolytic in parallel with 0.1 m F.
I DAC and ADC maximum reference. Bypass to VCMR with 10 m F in parallel with 0.1 m F.
I Analog VCC, 5 V.
O Right channel output.
O Left channel output.
I Microphone input 1.
I Microphone input 2.
I Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to ana-
log ground with 0.1 m F.
I DAC and ADC minimum reference. Bypass to VCMR with 10 m F in parallel with 0.1 m F.
I Full scale DAC current adjustment.
I Compensation pin.
I Video Analog Ground
O Modulated chrominance output.
I Video VCC, 5 V
O Y luminance data bus for screen video port.
O Composite video output.
I Audio CAP
O Crystal output.
I 27 MHz crystal input.
I/O 13.5 MHz pixel clock.
I/O 27 MHz (2 times pixel clock).
O Horizontal sync (active-low).
O Vertical sync (active-low).
I YUV data bus for screen video port.
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