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CHAPTER 2 CPU
2.2
Hardware Structure
This section explains the hardware structure of the CPU and the 16FX core.
■ Hardware Structure of the CPU
●
CPU Block Diagram
Fetch stage
Decode stage 1
Decode Stage 2
Execution stage
Write Back stage
●
CPU Pipeline Operation
To execute most instructions in one clock cycle, the CPU uses a five-stage instruction pipeline. The pipeline
consists of the following stages:
• Instruction fetch (IF): Fetches the instruction from instruction queue.
• Instruction decode 1 (D1): Decodes the instruction and controls address operation.
• Instruction decode 2 (D2): Decodes the instruction and selects operands and data operation.
• Execution (EX): Executes the operation.
50
Figure 2.2-1 CPU block diagram
Instruction
Queue
Decode Address
Operation
Decode Data
Operation
Processor Status
PS
Stack Pointer
USP, SSP
Bank Register
USB, SSB, DTB, ADB
MB96300 Super Series Hardware Manual
F2MC−16FX CPU
Program Counter
PCB, PC
ALU
Accumulator
AH, AL
General−Purpose
Register
Ri, RWi, RLi
Direct Page Register
DPR
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