Sharp 27DV-S100 Service Manual page 90

IC702 IX3420CE 4M EDO DRAM
Terminal Terminal name
16-19, 22-26 A -A
0 8
14 RAS
28 UCAS
29 LCAS
13 WE
27 OE
2-5, 7-10 DQ -DQ
1
31-34, 36-39
1, 6, 20 V
CC
21, 35, 40 V
SS
11-12, 15, 30 NC
• Block Diagram
OE
WE
UCAS
LCAS
RAS
V
CC
V
SS
A0
A1
Address buffers
and predecoders
A7
A8
Address inputs.
Row address strobe.
Column address strobe/upper byte control.
Column address strobe/lower byte control.
Write enable.
Output enable.
Data inputs/outputs.
16
+3.3V power supply.
0V ground.
No connection.
RAS clock CAS clock
generator generator
Column decoders
Refresh
Sense amplifiers
counter
Y -Y
0 8
9
Row
decoders
X -X
0 8
Function
WE clock OE clock
generator generator
Data I/O Bus
I/O
512 16
Buffer
Memory
array
512
91
27DV-S100
27DV-CS10
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16