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External Bus Interface
13.4.7.3.6 Burst Data in Progress Signal. The BDIP signal is sent from the master to the
slave to indicate that there is a data beat following the current data beat. The master uses
this signal to give the slave advanced warning of the remaining data in the burst. By negating
the BDIP signal, you can terminate a burst cycle early. Refer to Section 13.4.2 Single Beat
Transfers and Section 13.4.4 The Burst Mechanism for more information.
13.4.8 Data Transfer Phase-Related Signals
13.4.8.1 DATA SIGNAL. The D[0:31] signals are driven by the MPC823e when it owns the
external bus and has initiated a write transaction to a slave device. During a read transaction
the D[0:31] signals are driven by the slave device. See Table 13-2 for byte lane
assignments.
13.4.9 Termination Phase-Related Signals
13.4.9.1 TRANSFER ACKNOWLEDGE SIGNAL. The TA signal indicates the normal
completion of a bus transfer. During burst cycles, the slave asserts this signal with every
data beat returned or accepted. This signal must be pulled up to V
with a pull-up resistor.
DD
13.4.9.2 BURST INHIBIT SIGNAL. The BI signal is sent from the slave to the master to
indicate that the addressed device does not have burst capability. If this signal is asserted
or equal to 0, the master must transfer in multiple cycles and increment the address for the
slave to complete the burst transfer. For a system that does not use the burst mode at all,
this signal can be permanently tied low. This signal must be pulled up to V
with a pull-up
DD
resistor.
13.4.9.3 TRANSFER ERROR ACKNOWLEDGE SIGNAL. The TEA signal terminates the
bus cycle under bus error conditions. The current bus cycle must be aborted. This signal
must override any other cycle termination signals, such as the TA signal. This signal must
be pulled up to V
with a pull-up resistor.
DD
13-36
MPC823e REFERENCE MANUAL
MOTOROLA
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