Defect Circuit - Pioneer PD-7050 Service Manual

Note that since this EFM Comparator is of
power-current SW type, its H and L levels will not
equal the supply voltage, there is feedback via the
decoder's C-MOS Buffer.
R2Q, R21, CI6, and C17 serve as a LPF for
obtaining the DC of (Vcc + DGND)/2 [V].
DEFECT CIRCUIT
After inverting the RFI signal, the Defect circuit
performs Bottom Hold using two time constants, one
long and one short. The Bottom Hold performed by
the short time constant sends a response at a
mirror-surface defect on the disc that is 0.1 ms or
longer. The Bottom Hold performed using the long
time constant continues holding the mirror surface
at the level preceding the defect. The Mirror
Defect Detection signal is generated by performing
a fine plus level shift of that mirror level by use of
C coupling, then making a comparison of both
signals.
When this signal is used and the DEFECT output is
"H," TRKG error is muted and the payability is
improved.
Fig. 4-19