Hitachi 51SWX20B Training page 35

DP-2X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION
PinP Tuner U302 (monaural only, but audio not used).
The Microprocessor controls the Main Tuner by SDA2 (Data) and SCL2 (Clock) I
SCL2 and SDA2 lines for the Main Tuner are output from the Microprocessor at pins (31 SDA2 and 28 SCL2)
respectively. These lines go directly to the Main Tuner, SDA2 at pin (5) and SCL2 at pin (4). These lines control
band switching, programmable divider set-up information, pulse swallow tuning selection, etc...
EEPROM I003
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List, Cus-
tomer set ups for Video, Audio, Surround etc... are memorized as well. Also, some of the Microprocessors inter-
nal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption detection.
Data and Clock lines are SDA1 from pin (30) of the Microprocessor to pin (5) of the EEPROM and SCL1 from
pin (29) of the Microprocessor to pin (6) of the EEPROM. Data travels in both directions on the Data line.
Flex Converter FC04
The projection television is capable of displaying NTSC as well as ATSC (SDTV) including HD (High Defini-
tion). The Flex Converter is responsible for receiving any video input and converting it to 33.75 Khz output. This
output is controlled by sync and by the customer's menu and how it is set up. The set up can be 4X3 or 16X9 for
DTV, or letterbox. This set also has something called "16X9 Normal Mode". This bypasses the Flex Converter
completely and inputs the 1080i signal directly to the Rainforest IC I401. The Flex Converter can take any
NTSC, S-In, Component, NTSC or Progressive, Interlaced, 480I, 720P, 1080i signal.
Control for the Flex Converter is Clock, Data and Enable lines.
Clock, Data and Enable lines for the Flex Converter are output from the Microprocessor at pins (52 Data, 53
Clock and 55 FCENABLE). The FCENABLE line is routed through the PFC1 connector pin 12 and the
FCDATA line is routed through the PFC1 connector pin 11, the FC Clock is routed through the PFC1 connector
pin 10.
The Clock, Data and Enable lines must be routed through the Level Shift IC I007 to be brought up to 5V.
Clock is input to I007 at pins (2 Clock) and is output at pins (18).
Data is input to I007 at pins (4 Clock) and is output at pins (16).
Enable is input to I007 at pins (6 Clock) and is output at pins (14).
Data from the Flex Converter is also sent back to the Microprocessor. Data from the Flex is sent out of the PFC1
connector pin 11 to pin 5 of I007, level shifted down to 3.3V and output at pin 15 into pin 51 of the Microproces-
sor I001.
Level Shift I007
The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at 5Vdc.
The Level Shift IC steps up the DC voltage to accommodate.
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Pin 18 outputs a Clock signal, used by the Flex Converter
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Pin 14 outputs an Enable signal, used by the Flex Converter
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Pin 16 outputs a Data signal, used by the Flex Converter.
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Pin 15 outputs Data, sent from the Flex Converter
Rainforest I401 (Video/Chroma Processor)
The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the signal is
made available to the CRTs. Some of the emphasis circuits are controlled by the customer's menu. As well as
some of them being controlled by AI, (Artificial Intelligence).
Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to the Rainforest IC pins (31 and 30)
respectively.
BBE Control IA01 (Surround)
The DP-2X chassis utilizes BBE Surround.
Communication from the Microprocessor via pins (31 SDA2 and 28 SCL2) to the BBE IC pins (13 and 14) re-
spectively.
2
C communication lines.
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