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Raven PCI Bridge ASIC
2
Entity Addressed
PIACK
CONADD/CONDAT
MPC Mapped PCI Space
MPC Mapped PCI Space
2-18
The PCI master can support Critical Word First (CWF) burst transfers. The
PCI master will divide this transaction into two parts. The first part will
start on the address presented with the CWF transfer request and continue
up to the end of the current cache line. The second transfer will start at the
beginning of the associated cache line and work its way up to (but not
including) the word addressed by the CWF request.
It should be noted that even though the master can support burst
transactions, a majority of the transaction types handled are single-beat
transfers. Since PCI space is typically not configured as cacheable, burst
transactions to PCI space would not naturally occur. Burst transactions
must be supported, however, since it is conceivable that bursting could
happen. For example, nothing prevents the processor from loading up a
cache line with PCI write data and manually flushing the cache line.
The following paragraphs identify some associations between the
operation of the PCI master and the requirements of the PCI 2.0 Local Bus
Specification.
Command Types
The PCI command codes generated by the PCI master depend on the type
of transaction being performed on the MPC bus. Please refer to the MPC
Slave section earlier in this chapter for a further description of MPC bus
read and MPC bus write transactions.
types supported and shows how they are generated.
Table 2-5. PCI Master Command Codes
MPC
Transfer Type
Read
Write
Read
Write
-- Unsupported --
-- Unsupported --
Read
Write
Table 2-5
TBST
MEM
C/BE
x
x
0000
x
x
0001
x
0
0010
x
0
0011
0100
0101
1
1
0110
x
1
0111
Computer Group Literature Center Web Site
summarizes the command
PCI Command
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
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