System Control Block Diagram - Sony DVP-PQ2 Service Manual

DVP-PQ2

3-2. SYSTEM CONTROL BLOCK DIAGRAM

MB-108 BOARD (1/5)
(SEE PAGE 4-9)
HA 0 – 21 HA 0 – 21
HD 0 – 15 HD 0 – 15
XRD
XWRH
SIGNAL PROCESSOR
(SEE PAGE 3-5)
XARPIT
XARPCS
XWAIT
XRST
XRST
XSDPIT
XSDPCS
RF/SERVO
XDRVMUTE
(SEE PAGE 3-4)
XLDON
XAVDIT
DREQ0
DACK0
DREQ1
DACK1
XAVDCS2
XAVDCS3
XFRRST
SIGNAL PROCESSOR
(SEE PAGE 3-5)
33MARP
27MAVD
512FSAVD
05
IC106 IC107
or
16M FLASH OTP
58 59 72 84
1 – 5 102 – 109 111 – 118 120 85 – 100
HA 0 – 21 HD 0 – 15
70 XRD
71 XWRH
17 INT1
62 CS4X
67 XWAIT
35 XRST
18 INT2
63 CS5X
IC104
48 XDRVMUTE
82 WIDE
SYSTEM
CONTROL
IC101
EEPROM
WP 7 7 WP
SCL 6 39 SCL
SDA 5 38 SDA
16 INTO
46 DREQ0
47 DACK0
49 DREQ1
50 DACK1
60 CS2X
61 CS3X
81
IC103
4
IC103 qg
PLL
14 FSEL
3.3Vp-p
30nsec
15 33-1OUT 512-2OUT
3 27-1OUT 512-1OUT
3-3
5
IC104 tf
3.3Vp-p
X1 60nsec
53
X101
16.5MHz
X0
54
XARPRST 36
SI0 25
SO0 26
SCO 27
XIFCS 51
INT4 20
XFRRST 76
MA MUTE 83
SO1 29
SC1 30
XDACS 79
2
IC103 8
3
IC103 9 q;
3.3Vp-p
38nsec
XTI
7
X102
27MHz
XTO 8
42nsec
9
10
1
IC103 3
3.3Vp-p
1.17msec
VIDEO/AUDIO
WIDE
(SEE PAGE 3-10)
CN101
4
1
3
6
5
8
MA MUTE
SO1
SC1
XDACS
AUDIO/VIDEO
XRST
(SEE PAGE 3-9)
3.3Vp-p
512FS2CH
3-4
SI0
SO0
INTERFACE
SC0
CONTROL
XIFCS
(SEE PAGE 3-11)
XIFBUSY
XFRRST