Sony CDX-C8850R Service Manual page 31

Pin No. Pin Name
74 SIN
75 BCK
76 LRCK
77 XMST
78 VDD3
79 AVSP
80 PLLEN
81 PLCLK
82 CKSTP
83 AVDP
84 VSS4
85 – 94 TD14 – 23
95 VDD4
96 AVSD
97 SCLI
98 BIM
99 SDRAM
100 AVDD
I/O
I Serial data input (Fixed at "L" in this set.)
I Clock signal input for serial bit transfer of serial input/output data.
I Sampling frequency clock signal input of serial input/output data.
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select
I
signal input from system control (IC500). ("L" : master mode, "H" : slave mode)
— Digital power supply pin (+3.3 V)
— PLL system ground
I PLL enable signal input (Normally, fixed at "L".)
O PLL clock signal output (Not used in this set.)
I PLL clock output control signal input from system control (IC500).
— PLL system power supply pin (+3.3 V)
— Digital ground
I Test pin (Normally, fixed at "L".)
— Digital power supply pin (+3.3 V)
— Ground (for D-RAM)
I Not used. (Normally, fixed at "L".)
I Not used. (Normally, fixed at "L".)
I Not used. (Normally, fixed at "L".)
— Power supply pin (+3.3 V) (for D-RAM)
Pin Description
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