Sanyo DVD1451U Service Manual page 28

Block Diagram
Pin Descriptions
Symbol
CLk System Clock
CS Chip Select
CKE Clock Enable
A0~A10/AP
BA Bank Select Address
RAS Row address Strobe
CAS
Column Address Strobe
WE Write Enable
L(U)DQM
Data Input/Output Mask
DW0-15 Data Input/Output
VDD/VSS Power Supply/Ground
Data Output
VDDQ/VSSQ
Power/Ground
NC/RFU No Connection
Name
Active on the positive going edge to sample all inputs
Disables or Enables device operation by masking or enabling
all inputs except CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new
command.
Disable input buffers for power down in standby.
Row/Column addresses are multiplexed on the same pins.
Address
Row address: RA0 ~ RA10, Column address: CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low. Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
Description
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