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HP 27130B
Register 3 - DMA B Configuration.
The functions of the bits of register 3 (read/write) are as
follows:
Bit 7
=
Dl\1A channel B enable bit
1
=
enable
o
=
disable
Bit 6
=
Transfer to/from memory
1
=
to memory
o
=
from memory
Bit 5
=
Direction of memory address counter
1
=
decrement counter
o
=
increment counter
Bit 4
=
D:LvtA channel B interrupt enable
Bit 3
1
=
enable interrupt
o
=
disable interrupt
Bit 2
Upper four bits of transfer byte count for DMA B
Bit 1
Bit 0
NOTE
Bits 4 through 7 are zeroed on reset. Bits 0 through
3 are not affected by reset.
Register 4 - Lower Byte of Transfer Byte Count - Channel B. Register 4 (read/write) contains the
lower byte of the transfer byte count for channel
B.
This register is not affected by reset.
Register 5 - DMA B I/O Port Address. Register
5 (read/write) contains the DMA B I/O port ad-
dress. This register is not affected by reset.
Register 6 - DMA A Upper Byte of Memory Address.
Register 6 (write only) contains the upper
byte of the memory address used as a source/destination for channel A. Note that this register is not
affected by reset.
Register 7 - DMA A Lower Byte of Memory Address.
Register 7 (write only) contains the lower
byte of the memory address used as a source/destination for channel A. Note that this register is not
affected by reset.
3-26
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