LG 55LM9600 Service Manual page 61

L9 Block diagram
xi_main
24Mhz
xo_main
About 220 internally generated clocks
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
30/48 Mhz
2 port USB PHY
30/48Mhz
1 port USB PHY
1 Ghz
DDR3PLL
SSC setting
- 0xFD3001D4
- 0xFD3001D8
CT
R
1.6Ghz
DDR3PLL1
SSC setting
- 0xFD3001CC
- 0xFD3001D0
DDR3PLL2
1.6Ghz
SSC setting
- 0xFD3001C4
- 0xFD3001D8
de_dco_ou
DCO
t
Glitch-free logic
27Mhz
200Mhz
between
de_dco_out and
sdec_dco_o
sdec_dco_out
DCO ut
27Mhz
200Mhz
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
1.6Gh
z
i_m01_ddrclk
1.6Ghz
Clock Divide & Reset generation
i_m2_ddrclk
w/ test logic
800Mhz
i_core800_clk
1/2
800Mhz i_core320_clk
1/5
Clock Divide & Reset generation
w/ test logic
dcoin_clk
SSC setting
-0xFD300108
CT
-0xFD30010C
27Mhz
R
DISPLL
disp_fout
udnt_buf_dpll_fin
Clock Divide & Reset
u_DPLL
generation w/ test logic
27Mhz sclk
TE
USB controller
u_crg
CPU
Memory Controller
Memory Controller
Memory Controller
Video/Audio Block
CPU peripherial
DE
LGE Internal Use Only