CHAPTER 9 12-BIT PPG TIMER
9.4.3
12-bit PPG Control Register 3 (RCR23)
The 12-bit PPG control register 3 comprises a bit for enabling 12-bit PPG waveform
outputs and bits for setting a cycle period of outputs.
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12-bit PPG Control Register 3 (RCR23)
Address
bit7
bit6
0016
RCEN
H
R/W
:
Readable/Writable
R/W
: Unused
: Initial value
216
Figure 9.4-4 12-bit PPG Control Register 3 (RCR23)
bit5
bit4
bit3
bit2
SCL5 SCL4 SCL3 SCL2 SCL1 SCL0
R/W
R/W
R/W
R/W
SCL5 to SCL0
Compare value for the cycle period of 12-bit PPG output
XXXXXX
RCEN
0
Output disabled, counter cleared
Output enabled with count operation starting
1
bit1
bit0
Initial value
0-000000
B
R/W
R/W
Cycle period setting bits
Output enable bit