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Generation
Of
the
The logic analyzer stores the state of the data and status lines whenever it
Logic Analyzer
receives the falling edge of its dock. Setup and Hold times are referenced
ClOCkS
to
e^8e- There are four conditions in which the logic analyzer
receives a clock:
•
Arbitration phase;
•
Select or Reselect phase;
•
Information phase that is sent with handshake lines; and
•
When Reset and Bus Free occurs at the same time.
Arbitration Phase. The analyzer clock gets a negative transition when
both the Busy and Select lines go active, ending the SCSI Arbitration
phase. This is accomplished with the NAND Gate U17D. The clock
pulse is a 40nS pulse that is generated with the delay through the
comparitors U13A/B or U14A/B, depending on whether the Single-ended
or Differential mode is selected.
Select or Reselect Phase. The analyzer clock for the Select or Reselect
phase is generated by Busy being low and Select being active or high This
is accomplished with the AND Gate U17A and by
inverting
Busy with
U10F.
ARBITRATION
PHASE
SELECT/RESELECT
PHASE
SELECT
J CLK
ANALYZER CLK
ANALYZER CLK
INF
FOR ARBITRATION
FOR SELECT OR
COES
MISC/10343*02
PHASE
RESELECT
TRUE
PHASE
Figure A-3. HP 10343B Timing
Additional Information
A-ll
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