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TRC-70
MAT-100 (AUTOMATIC ANTENNA TUNER)
¢
Frequency read block
The HF signal obtained by the sensor circuit is passed
'through a limiter consisting of C18, C21, D6, and D7,
then sent to frequency divider 1C1 (1/16) (wPB553AC).
The output level of IC1 is ECL level, so it is converted
to TTL level by buffer amplifier Q9, then fed to counter
C2.
The CPU controls the counter at the timing shown
in the Figure 4. The counter is cleared with a reset
signal, a pulse of this duration is counted with a gate
signal, and the count value is latched with a load signal.
Meanwhile, data is sent from terminals 1 through 4.
For terminals 10°, 10', 107, and 10°, a digit signal to
indicate the data digit is output in an internal free-run-
ning period of approximately 700 Hz.
IC3 is used to
Ci
c2
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I
RET
LOAD
C1: Furequency signal
C2: Gate signal
RET : Reset signal
LOAD : LOAD signal
Fig. 4 Counter control timing chart
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Fig. 5 Frequency read block
112
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