5.3
External Bus Interface Function Timing
Timing control signal output pins in the external memory expansion mode are as follows.
(1) RD pin (Alternate function: P64)
Read strobe signal output pin. The read strobe signal is output in data read and instruction fetch from external
memory.
During internal memory read, the read strobe signal is not output (maintains high level).
(2) WR pin (Alternate function: P65)
Write strobe signal output pin. The write strobe signal is output in data write to external memory.
During internal memory write, the write strobe signal is not output (maintains high level).
(3) WAIT pin (Alternate function: P66)
External wait signal input pin.
When the external wait is not used, the WAIT pin can be used as an I/O port.
During internal memory access, the external wait signal is ignored.
(4) ASTB pin (Alternate function: P67)
Address strobe signal output pin.
instruction fetch from external memory.
During internal memory access, the address strobe signal is output.
(5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57)
Address/data signal output pins. Valid signal is output or input during data accesses and instruction fetches
from external memory.
These signals change even during internal memory access (output values are undefined).
The timing charts are shown in Figures 5-5 to 5-8.
CHAPTER 5 EXTERNAL BUS INTERFACE
The address strobe signal is output regardless of data access and
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