Page 1 Old Company Name in Catalogs and Other Documents On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document.
Page 2 Notice All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Page 3 User’s Manual V850/SC1 , V850/SC2 , V850/SC3 32-Bit Single-Chip Microcontrollers Hardware µ µ µ µ PD703068Y µ µ µ µ PD703069Y µ µ µ µ PD703088Y µ µ µ µ PD703089Y µ µ µ µ PD70F3089Y Document No. U15109EJ3V0UD00 (3rd edition) Date Published June 2002 N CP(K) ©...
Page 4 [MEMO] User’s Manual U15109EJ3V0UD...
Page 5 C system, provided that the system conforms to the I C Standard Specification as defined by Philips. V850 Series, V850/SC1, V850/SC2, V850/SC3, IEBus, and Inter Equipment Bus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 6 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 7 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 8 Major Revisions in This Edition (1/4) Page Description • Deletion of indication “under development” for the following products (developed) Throughout µ PD703068YGJ-×××-UEN, 703069YGJ-×××-UEN • Addition of watch timer high-speed clock select register (WTNHC), IIC flag registers 0 and 1 (IICF0, IICF1) p.49 Change of minimum instruction execution time in 1.4.1 Features (V850/SC3)
Page 9 Major Revisions in This Edition (2/4) Page Description p.288 Change of description of Caution in 8.2.6 (2) One-shot pulse output via external trigger p.319 Addition of Caution in 10.3 (2) Watchdog timer clock select register (WDCS) p.324 Addition of description in 11.2 (2) 3-wire serial I/O mode (fixed as MSB first) p.327 Addition to Cautions in 11.2.2 (1) Serial clock select register n (CSISn) and serial operation mode register n (CSIMn)
Page 10 Major Revisions in This Edition (3/4) Page Description pp.479, 480 Addition of 13.5 Operation pp.480 to 482 Addition of 13.6 Cautions p.483 Modification of description in 14.1 (3) Internal reset by power-on-clear (POC) p.487 Modification of description in 14.3 (3) POC control register (POCC) p.495 Addition of Figure 17-1 Example of Wiring of Adapter for Flash Programming (FA-144GJ-UEN) Addition of Table 17-1 Table for Wiring of Adapter for µ...
Page 11 Major Revisions in This Edition (4/4) Page Description p.630 Addition of Caution in 19.7 Time Stamp Function p.633 Modification of description in 19.8 Message Processing p.638 Change of Figure 19-10 Composition of Layers p.653 Addition of Caution in 19.11.7 (2) Nominal bit time (8 to 25 time quanta) p.654 Addition to Note in Figure 19-25 Nominal Bit Time p.656...
Page 12 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850/SC1, V850/SC2, and V850/SC3 to design application systems using the V850/SC1, V850/SC2, and V850/SC3. Purpose This manual is intended to give users an understanding of the hardware functions described in the Organization below.
Page 13 Conventions Data significance: Higher digits on the left and lower digits on the right Active low: xxx (overscore over pin or signal name) Memory map address: Higher addresses at the top and lower addresses at the bottom Note: Footnote for items marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Number representation: Binary …...
Page 14 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850/SC1, V850/SC2, V850/SC3 Document Name Document No. V850 Series Architecture User’s Manual U10243E V850/SC1, V850/SC2, V850/SC3 Hardware User’s Manual This manual Documents related to development tools (user’s manuals) Document Name...
Page 15: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION.........................34 General ............................34 V850/SC1 ...........................35 1.2.1 Features (V850/SC1) ....................... 35 1.2.2 Application fields (V850/SC1) ....................36 1.2.3 Ordering information (V850/SC1)..................... 36 1.2.4 Pin configuration (top view) (V850/SC1) .................. 37 1.2.5 Function blocks (V850/SC1) ....................39 V850/SC2 ...........................42 1.3.1 Features (V850/SC2) .......................
Page 16 3.4.7 Recommended use of address space ..................106 3.4.8 Peripheral I/O registers ......................108 3.4.9 Specific registers ........................118 CHAPTER 4 CLOCK GENERATION FUNCTION................120 General.............................120 Configuration ..........................121 Clock Output Function ......................121 4.3.1 Control registers ........................122 Power Save Functions ......................125 4.4.1 General...........................125 4.4.2 HALT mode ..........................126 4.4.3 IDLE mode..........................129 4.4.4...
Page 17 6.2.2 Control register........................201 Bus Access ..........................201 6.3.1 Number of access clocks ....................... 201 6.3.2 Bus width..........................202 Memory Block Function......................203 Wait Function..........................204 6.5.1 Programmable wait function....................204 6.5.2 External wait function ......................205 6.5.3 Relationship between programmable wait and external wait ..........205 Idle State Insertion Function ....................206 Bus Hold Function........................207 6.7.1...
Page 18 7.5.2 Operation..........................244 7.5.3 Restore...........................245 Priority Control........................246 7.6.1 Priorities of interrupts and exceptions ..................246 7.6.2 Multiple interrupt servicing......................247 Response Time ........................249 Periods in Which Interrupts Are Not Acknowledged ............250 7.8.1 Interrupt request valid timing following EI instruction .............250 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer ....252 7.10 Key Interrupt Function ......................253 CHAPTER 8 TIMER/COUNTER FUNCTION..................255...
Page 19 CHAPTER 10 WATCHDOG TIMER FUNCTION.................316 10.1 Functions ..........................316 10.2 Configuration ..........................318 10.3 Watchdog Timer Control Registers ..................318 10.4 Operation..........................321 10.4.1 Operation as watchdog timer ....................321 10.4.2 Operation as interval timer ..................... 322 10.5 Standby Function Control Register..................323 CHAPTER 11 SERIAL INTERFACE FUNCTION................324 11.1 Overview..........................324 11.2 3-Wire Serial I/O (CSI0, CSI2, CSI3): 8 Bits................324...
Page 20 11.6.4 Standby function........................453 CHAPTER 12 A/D CONVERTER......................454 12.1 Function...........................454 12.2 Configuration ..........................456 12.3 Control Registers........................458 12.4 Operation ..........................461 12.4.1 Basic operation........................461 12.4.2 Input voltage and conversion result..................463 12.4.3 A/D converter operation mode....................464 12.5 Low-Power-Consumption Mode....................467 12.6 Cautions...........................467 CHAPTER 13 DMA FUNCTIONS ......................471 13.1 Functions..........................471 13.2 Transfer Completion Interrupt Request................471 13.3 Configuration ..........................472...
Page 21 17.3 Programming Environment ....................497 17.4 Communication Mode ......................497 17.5 Pin Connection ........................500 17.5.1 pin............................ 500 17.5.2 Serial interface pin ......................... 501 17.5.3 RESET pin ..........................503 17.5.4 Port pins (including NMI)......................503 17.5.5 Other signal pins ........................503 17.5.6 Power supply.......................... 503 17.6 Programming Method ......................504 17.6.1 Flash memory control......................
Page 22 19.4 Internal Registers of FCAN Controller..................562 19.4.1 Configuration of messages and buffers..................562 19.4.2 List of FCAN registers ......................563 19.5 Control Registers........................576 19.5.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) ........576 19.5.2 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31)........577 19.5.3 CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31)......579 19.5.4...
Page 23 19.11.1 Determination of bus priority ....................649 19.11.2 Bit stuffing ..........................649 19.11.3 Multimasters........................... 649 19.11.4 Multi-cast..........................649 19.11.5 CAN sleep mode/CAN stop mode function ................650 19.11.6 Error control function......................650 19.11.7 Baud rate control function ...................... 653 19.12 Operations..........................656 19.12.1 Initialization processing ......................
Page 24 LIST OF FIGURES (1/8) Figure No. Title Page CPU Register Set ............................87 CPU Address Space............................93 Address Space Imaging ..........................94 Program Space..............................95 Data Space..............................95 Memory Map..............................96 Internal ROM/Flash Memory Area ........................97 Internal RAM Area ............................99 On-Chip Peripheral I/O Area .........................100 3-10 External Memory Area (When Expanded to 64 KB, 256 KB, or 1 MB)............101 3-11 External Memory Area (When Expanded to 4 MB)..................102...
Page 25 LIST OF FIGURES (2/8) Figure No. Title Page Byte Access (8 Bits) ............................202 Halfword Access (16 Bits) ..........................202 Word Access (32 Bits)........................... 202 Memory Block..............................203 Wait Control..............................205 Example of Inserting Wait States ........................205 Bus Hold Procedure ............................208 Memory Read..............................
Page 26 LIST OF FIGURES (3/8) Figure No. Title Page Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register .................................276 Configuration for Pulse Width Measurement with Free-Running Counter.............277 8-10 Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) ............................277 8-11 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter.....278...
Page 27 LIST OF FIGURES (4/8) Figure No. Title Page 10-1 Block Diagram of Watchdog Timer........................ 316 11-1 Block Diagram of 3-Wire Serial I/O (CSI0, CSI2, CSI3) ................325 11-2 CSIMn Setting (Operation Stopped Mode)....................328 11-3 CSIMn Setting (3-Wire Serial I/O Mode) ....................... 329 11-4 Timing of 3-Wire Serial I/O Mode ........................
Page 28 LIST OF FIGURES (5/8) Figure No. Title Page 11-37 Master Operation Flowchart (1)........................424 11-38 Master Operation Flowchart (2)........................425 11-39 Slave Operation Flowchart ..........................426 11-40 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ................428 11-41 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ................431...
Page 29 LIST OF FIGURES (6/8) Figure No. Title Page Regulator ( µ PD70F3089Y)..........................488 15-1 16-1 Block Diagram of ROM Correction ........................ 489 16-2 ROM Correction Operation and Program Flow ..................... 492 17-1 Example of Wiring of Adapter for Flash Programming (FA-144GJ-UEN)............495 17-2 Environment Required for Writing Programs to Flash Memory ..............
Page 30 LIST OF FIGURES (7/8) Figure No. Title Page 18-21 Master Transmission (Interval of Interrupt Occurrence) ................555 18-22 Master Reception (Interval of Interrupt Occurrence) ..................556 18-23 Slave Transmission (Interval of Interrupt Occurrence) ..................557 18-24 Slave Reception (Interval of Interrupt Occurrence) ..................558 19-1 Block Diagram of FCAN ..........................561 19-2...
Page 31 LIST OF FIGURES (8/8) Figure No. Title Page 19-34 Setting of CANn Interrupt Enable Register (CnIE) ..................660 19-35 Setting of CANn Definition Register (CnDEF) ....................661 19-36 Setting of CANn Control Register (CnCTRL) ....................662 19-37 Setting of CANn Address Mask a Registers L and H (CnMASKLa and CnMASKHa)........663 19-38 Message Buffer Setting ..........................
Page 32 LIST OF TABLES (1/4) Table No. Title Page Product Lineup of V850/SC1, V850/SC2, and V850/SC3 ................34 Pin I/O Buffer Power Supplies .........................56 Differences in Pins of V850/SC1, V850/SC2, and V850/SC3................57 Pin Operation States in Various Operating Modes..................66 Program Registers............................88 System Register Numbers..........................89 Interrupt/Exception Table ..........................98 Operating Statuses in HALT Mode........................127 Operating Statuses in IDLE Mode .........................129...
Page 33 LIST OF TABLES (2/4) Table No. Title Page Description of Key Return Detection Pin ....................... 253 Configuration of Timers 0, 1, and 7 to 12 ...................... 257 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ................... 258 Valid Edge of TIn1 Pin and Capture Trigger of CRn0 ................... 258 Valid Edge of TIn0 Pin and Capture Trigger of CRn1 ...................
Page 34 LIST OF TABLES (3/4) Table No. Title Page Table for Wiring of Adapter for µ PD70F3089Y Flash Programming (FA-144GJ-UEN) .........496 17-1 17-2 Signal Generation of Dedicated Flash Programmer (PG-FP3)..............499 17-3 Pins Used by Serial Interfaces ........................501 17-4 List of Communication Modes ........................505 17-5 Flash Memory Control Commands ........................506 17-6...
Page 35 LIST OF TABLES (4/4) Table No. Title Page 19-19 Data Length Code Settings ........................... 642 19-20 Operation in Error Status..........................646 19-21 Operation When Third Bit of Intermission Is Dominant Level................ 646 19-22 Field Definitions of Error Frame ........................647 19-23 Field Definition of Overload Frame........................
Page 36: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850/SC1, V850/SC2, and V850/SC3 are products in NEC’s V850 Series of single-chip microcontrollers designed for low-power operation. 1.1 General The V850/SC1, V850/SC2, and V850/SC3 are 32-bit single-chip microcontrollers that include the V850 Series’ CPU core, and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a DMA controller.
Page 37: V850/Sc1
CHAPTER 1 INTRODUCTION 1.2 V850/SC1 1.2.1 Features (V850/SC1) Number of instructions: Minimum instruction execution time 50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 100 ns (operating at 20 MHz) Instruction set (Able to execute instructions in parallel continuously without creating any register hazards)
Page 38: Application Fields (V850/Sc1)
CHAPTER 1 INTRODUCTION Serial interfaces (SIO) Asynchronous serial interface (UART) 3-wire serial I/O (CSI) C bus interface (I 8- to 16-bit variable-length serial interface CSI (8-bit)/UART: 1 channel CSI (8- to 16-bit variable)/UART: 1 channel CSI (8-bit)/I 2 channels CSI (8- or 16-bit): 2 channels UART: 2 channels...
Page 39: Pin Configuration (Top View) (V850/Sc1)
CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (top view) (V850/SC1) 144-pin plastic LQFP (20 × 20) • µ PD703068YGJ-×××-UEN • µ PD70F3089YGJ-UEN P80/ANI8 P141/SO3/TXD1 P81/ANI9 P140/SI3/RXD1 P82/ANI10 P133 P83/ANI11 P132 PORTGND0 P131 P40/AD0 P130 P41/AD1 PORTV P42/AD2 P127/TO11 P43/AD3 P126/TO10 P44/AD4 P125/SO6 P45/AD5 P124/SI6...
Page 40 CHAPTER 1 INTRODUCTION Pin names (V850/SC1) A1 to A21: Address bus P120 to P127: Port 12 AD0 to AD15: Address/data bus P130 to P133: Port 13 ADCGND: Ground for analog P140 to P147: Port 14 ADCV Power supply for analog P150 to P157: Port 15 ADTRG:...
Page 41: Function Blocks (V850/Sc1)
CHAPTER 1 INTRODUCTION 1.2.5 Function blocks (V850/SC1) (1) Internal block diagram HLDRQ (P96) INTC Instruction INTP0 to INTP9 HLDAK (P95) correction queue ASTB (P94) TI00, TI01,TI10, TI11 DSTB/RD (P93) TI70, TI71, TI80, TI81 32-bit barrel Timer counter Multiplier TI90, TI91, TI100, TI101 R/W/WRH (P92) 16 ×...
Page 42 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 43 CHAPTER 1 INTRODUCTION (j) Serial interfaces (SIO) The V850/SC1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTm), a 3- wire serial I/O (CSIn), and an I C bus interface (I Cx), which can use up to eight channels at the same time.
Page 44: V850/Sc2
CHAPTER 1 INTRODUCTION 1.3 V850/SC2 1.3.1 Features (V850/SC2) Number of instructions: Minimum instruction execution time 53 ns (operating at 18.87 MHz, external power supply 5 V, regulator output 3.3 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 106 ns (operating at 18.87 MHz) Instruction set (Able to execute instructions in parallel continuously without creating any register hazards)
Page 45: Application Fields (V850/Sc2)
CHAPTER 1 INTRODUCTION Serial interfaces (SIO) Asynchronous serial interface (UART) 3-wire serial I/O (CSI) C bus interface (I 8- to 16-bit variable-length serial interface CSI (8-bit)/UART: 1 channel CSI (8- to 16-bit variable)/UART: 1 channel CSI (8-bit)/I 2 channels CSI (8- or 16-bit): 2 channels UART: 2 channels...
Page 46: Pin Configuration (Top View) (V850/Sc2)
CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (top view) (V850/SC2) 144-pin plastic LQFP (20 × 20) • µ PD703069YGJ-×××-UEN • µ PD70F3089YGJ-UEN P80/ANI8 P141/SO3/TXD1 P81/ANI9 P140/SI3/RXD1 P82/ANI10 P133 P83/ANI11 P132 PORTGND0 P131 P40/AD0 P130 P41/AD1 PORTV P42/AD2 P127/TO11 P43/AD3 P126/TO10 P44/AD4 P125/SO6 P45/AD5 P124/SI6...
Page 47 CHAPTER 1 INTRODUCTION Pin names (V850/SC2) A1 to A21: Address bus P100 to P107: Port 10 AD0 to AD15: Address/data bus P110 to P117: Port 11 ADCGND: Ground for analog P120 to P127: Port 12 ADCV Power supply for analog P130 to P133: Port 13 ADTRG:...
Page 48: Function Blocks (V850/Sc2)
CHAPTER 1 INTRODUCTION 1.3.5 Function blocks (V850/SC2) (1) Internal block diagram HLDRQ (P96) INTC Instruction INTP0 to INTP9 HLDAK (P95) correction queue ASTB (P94) TI00, TI01,TI10, TI11 DSTB/RD (P93) TI70, TI71, TI80, TI81 32-bit Multiplier Timer counter TI90, TI91, TI100, TI101 R/W/WRH (P92) 16 ×...
Page 49 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 50 CHAPTER 1 INTRODUCTION (j) Serial interfaces (SIO) The V850/SC2 includes four kinds of serial interfaces: an asynchronous serial interface (UARTm), a 3- wire serial I/O (CSIn), and an I C bus interface (I Cx), which can use up to eight channels at the same time.
Page 51: V850/Sc3
CHAPTER 1 INTRODUCTION 1.4 V850/SC3 1.4.1 Features (V850/SC3) Number of instructions: Minimum instruction execution time 50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 100 ns (operating at 16 MHz) Instruction set (Able to execute instructions in parallel continuously without creating any register hazards)
Page 52: Application Fields (V850/Sc3)
CHAPTER 1 INTRODUCTION Serial interfaces (SIO) Asynchronous serial interface (UART) 3-wire serial I/O (CSI) C bus interface (I 8- to 16-bit variable-length serial interface CSI (8-bit)/UART: 1 channel CSI (8- to 16-bit variable)/UART: 1 channel CSI (8-bit)/I 2 channels CSI (8- or 16-bit): 2 channels UART: 2 channels...
Page 53: Pin Configuration (Top View) (V850/Sc3)
CHAPTER 1 INTRODUCTION 1.4.4 Pin configuration (top view) (V850/SC3) 144-pin plastic LQFP (20 × 20) • µ PD703088YGJ-×××-UEN • µ PD703089YGJ-×××-UEN • µ PD70F3089YGJ-UEN P80/ANI8 P141/SO3/TXD1 P81/ANI9 P140/SI3/RXD1 P82/ANI10 P133 P83/ANI11 P132 PORTGND0 P131 P40/AD0 P130 P41/AD1 PORTV P42/AD2 P127/TO11 P43/AD3 P126/TO10 P44/AD4...
Page 54 CHAPTER 1 INTRODUCTION Pin names (V850/SC3) A16 to A21: Address bus P80 to P83: Port 8 AD0 to AD15: Address/data bus P90 to P96: Port 9 ADCGND: Ground for analog P100 to P107: Port 10 ADCV Power supply for analog P110 to P117: Port 11 ADTRG:...
Page 55: Function Blocks (V850/Sc3)
CHAPTER 1 INTRODUCTION 1.4.5 Function blocks (V850/SC3) (1) Internal block diagram HLDRQ (P96) INTC Instruction INTP0 to INTP9 HLDAK (P95) correction queue ASTB (P94) TI00, TI01,TI10, TI11 DSTB/RD (P93) TI70, TI71, TI80, TI81 32-bit Multiplier Timer counter TI90, TI91, TI100, TI101 R/W/WRH (P92) 16 ×...
Page 56 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 57 CHAPTER 1 INTRODUCTION (j) Serial interfaces (SIO) The V850/SC3 includes four kinds of serial interfaces: an asynchronous serial interface (UARTm), a 3- wire serial I/O (CSIn), and an I C bus interface (I Cx), which can use up to eight channels at the same time.
Page 58: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins in the V850/SC1, V850/SC2, and V850/SC3 are described below, divided into port pins and non-port pins. There are six types of pin I/O buffer power supplies: PORTV to PORTV , and ADCV .
Page 59 CHAPTER 2 PIN FUNCTIONS (b) Other than µ µ µ µ PD70F3089Y Power Supply Corresponding Pins Usable Voltage Range 3.0 V ≤ PORTV ≤ 5.5 V Note 1 PORTV P40 to P47, P50 to P57, P60 to P65, P90 to P96, CLKOUT 3.0 V ≤...
Page 60 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/4) Pin Name PULL Function Alternate Function Port 0 8-bit I/O port INTP0 Input/output can be specified in 1-bit units. INTP1 INTP2 INTP3 INTP4/ADTRG INTP5 INTP6 Port 1 SI0/SDA0 8-bit I/O port Input/output can be specified in 1-bit units. SCK0/SCL0 Only P10 and P12 can be specified as N-ch open-drain pins.
Page 61 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name PULL Function Alternate Function Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Port 5 8-bit I/O port Input/output can be specified in 1-bit units. AD10 AD11 AD12 AD13 AD14 AD15 Port 6 6-bit I/O port...
Page 62 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name PULL Function Alternate Function Note 1 Port 9 LBEN/WRL 7-bit I/O port UBEN Input/output can be specified in 1-bit units. Note 1 R/W/WRH Note 1 DSTB/RD ASTB HLDAK HLDRQ Note 1 P100 Port 10 KR0/TO7/A5 8-bit I/O port Note 1...
Page 63 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name PULL Function Alternate Function P140 Port 14 SI3/RXD1 8-bit I/O port P141 SO3/TXD1 Input/output can be specified in 1-bit units. P142 SCK3/ASCK1 P143 RXD2 P144 TXD2 P145 ASCK2 P146 TI100 P147 TI101 P150 Port 15 RXD3 8-bit I/O port...
Page 64 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name PULL Function Alternate Function Output Lower address bus used for external memory expansion P110/WAIT (V850/SC1 and V850/SC2 only) A2 to A4 P111 to P113 P100/KR0/TO7 P101/KR1/TI70 P102/KR2/TI00 P103/KR3/TI01 P104/KR4/TO0 P105/KR5/TI10 P106/KR6/TI11 P107/KR7/TO1 P34/TI71...
Page 65 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name PULL Function Alternate Function HLDAK Output Bus hold acknowledge output HLDRQ Input Bus hold request input IERX0 Input IEBus data input (V850/SC2 only) IETX0 Output IEBus data output (V850/SC2 only) INTP0 to INTP3 Input External interrupt request input (analog noise elimination) P01 to P04...
Page 66 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name PULL Function Alternate Function SCK4 Serial clock I/O (3-wire type) for variable-length CSI4 P15/ASCK0 SCK5 Serial clock I/O (3-wire type) for CSI5, CSI6 P120 SCK6 P123 SCL0 Serial clock I/O for I P12/SCK0 SCL1 Serial clock I/O for I P22/SCK2...
Page 67 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name PULL Function Alternate Function Note 1 TI70 Input External count clock input for TM7/ P101/A6 /KR1 external capture trigger input for TM7 Note 1 TI71 External capture trigger input for TM7 P34/A13 TI80 External count clock input for TM8/ external capture trigger input for TM8 TI81...
Page 68: Pin States
CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operation states of pins in various operating modes are described below. Table 2-3. Pin Operation States in Various Operating Modes Note 1 Operating Mode Reset HALT Mode/ IDLE Mode/ Bus Hold Bus Cycle Note 2 Idle State STOP Mode...
Page 69: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (port 0) ··· 3-state I/O P00 to P07 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as an NMI input, external interrupt request inputs, and the external trigger for the A/D converter.
Page 70 CHAPTER 2 PIN FUNCTIONS (2) P10 to P17 (port 1) ··· 3-state I/O P10 to P17 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the serial interface and timer/counter. P10 and P12 can be selected as normal output or N-ch open-drain output pins.
Page 71 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (port 2) ··· 3-state I/O P20 to P27 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the serial interface, timer/counter, and IEBus data.
Page 72 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (port 3) ··· 3-state I/O P30 to P37 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the timer/counter, an address bus (A13 to A15) for external memory expansion, and external interrupt request inputs.
Page 73 CHAPTER 2 PIN FUNCTIONS (5) P40 to P47 (port 4) ··· 3-state I/O P40 to P47 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as a time division address/data bus (AD0 to AD7) when memory is expanded externally.
Page 74 CHAPTER 2 PIN FUNCTIONS (7) P60 to P65 (port 6) ··· 3-state I/O P60 to P65 function as a 6-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as an address bus (A16 to A21) when memory is expanded externally.
Page 75 CHAPTER 2 PIN FUNCTIONS (9) P90 to P96 (port 9) ··· 3-state I/O P90 to P96 function as a 7-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as control signal output pins, and bus hold control signal output pins when memory is expanded externally.
Page 76 CHAPTER 2 PIN FUNCTIONS (vi) HLDAK (hold acknowledge) ··· Output This is the output pin for the acknowledge signal that indicates the high impedance status for the address bus, data bus, and control bus when the V850/SC1, V850/SC2, and V850/SC3 receive a bus hold request.
Page 77 CHAPTER 2 PIN FUNCTIONS (10) P100 to P107 (port 10) ··· 3-state I/O P100 to P107 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as timer/counter I/O pins, key return inputs, and an address bus (A5 to A12) for external memory expansion.
Page 78 CHAPTER 2 PIN FUNCTIONS (11) P110 to P117 (port 11) ··· 3-state I/O P110 to P117 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as FCAN data I/O pins, the control signal (WAIT) that inserts waits into the bus cycle and an address data bus (A1 to A4) for external memory expansion.
Page 79 CHAPTER 2 PIN FUNCTIONS (12) P120 to P127 (port 12) ··· 3-state I/O P120 to P127 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the serial interface, and outputs for the timer/counter.
Page 80 CHAPTER 2 PIN FUNCTIONS (14) P140 to P147 (port 14) ··· 3-state I/O P140 to P147 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the serial interface, and inputs for the timer/counter.
Page 81 CHAPTER 2 PIN FUNCTIONS (15) P150 to P157 (port 15) ··· 3-state I/O P150 to P157 function as an 8-bit I/O port in which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as I/O pins for the serial interface and the timer/counter. (a) Port function P150 to P157 can be set to input or output in 1-bit units using the port 15 mode register (PM15).
Page 82 CHAPTER 2 PIN FUNCTIONS (16) P170 to P176 (port 17) ··· 3-state I/O P170 to P176 function as a 7-bit I/O port in which input and output can be specified in 1-bit units. = 4.5 V monitor output. During 8-bit access of In addition to I/O port pins, these pins can also be used as V port 17, the highest bit is ignored during a write operation and is read as “0”...
Page 83 CHAPTER 2 PIN FUNCTIONS (25) PORTV to PORTV (power supply for port) These are positive power supply pins for I/O ports and alternate-function pins. (26) PORTGND0, PORTGND1 (ground for port) These are ground pins for I/O ports and alternate-function pins (except for the alternate-function ports of the bus interface).
Page 84: Pin I/O Circuit Types, I/O Buffer Power Supply And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins (1/3) Alternate Function I/O Circuit Type Recommended Connection Buffer Power Supply PORTV Input: Independently connect to PORTV PORTGND0, or PORTGND1 via a resistor. P01 to P03 INTP0 to INTP2 Output:...
Page 85 CHAPTER 2 PIN FUNCTIONS (2/3) Alternate Function I/O Circuit Type Recommended Connection Buffer Power Supply P70 to P77 ANI0 to ANI7 ADCV Independently connect to ADCV or ADCGND via a resistor. P80 to P83 ANI8 to ANI11 ADCV Note 1 LBEN/WRL PORTV Input:...
Page 86 CHAPTER 2 PIN FUNCTIONS (3/3) Alternate Function I/O Circuit Type Recommended Connection Buffer Power Supply P140 SI3/RXD1 PORTV Input: Independently connect to PORTV PORTGND0, or PORTGND1 via a resistor. P141 SO3/TXD1 Output: Leave open. P142 SCK3/ASCK1 P143 RXD2 P144 TXD2 P145 ASCK2 P146, P147...
Page 87: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 8-A Pullup P-ch enable Data P-ch Schmitt-triggered input with hysteresis characteristics IN/OUT N-ch Output disable Type 4 Type 9 P-ch Data P-ch Comparator N-ch − (threshold voltage) Output N-ch disable Input enable Push-pull output that can be set for high impedance output...
Page 88: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SC1, V850/SC2, and V850/SC3 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time: V850/SC1: 50 ns (@ 20 MHz internal operation) V850/SC2: 53 ns (@ 18.87 MHz internal operation) V850/SC3: 62.5 ns (@ 16 MHz internal operation) •...
Page 89: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850/SC1, V850/SC2, and V850/SC3 can be classified into two categories: a general- purpose program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850 Series Architecture User’s Manual.
Page 90: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 91: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Interrupt status saving registers These registers save the PC and PSW when an exception or interrupt occurs.
Page 92 CHAPTER 3 CPU FUNCTIONS (2) Program status word (PSW) (1/2) After reset: 00000020H ID SAT CY OV Reserved field (fixed to 0). Non-maskable interrupt (NMI) servicing status NMI servicing not under execution. NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables multiple interrupts.
Page 93 CHAPTER 3 CPU FUNCTIONS (2/2) Detection of operation result zero The operation result was not 0. The operation result was 0. Note The result of a saturation-processed operation is determined by the contents of the OV and S bits in the saturation operation.
Page 94: Operating Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operating Modes The V850/SC1, V850/SC2, and V850/SC3 have the following operating modes. (1) Normal operating mode (single-chip mode) After the system has been released from the reset state, the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal ROM, and the instruction processing written in the internal ROM is started.
Page 95: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space The CPU of the V850/SC1, V850/SC2, and V850/SC3 has 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, a linear address space (program space) of up to 16 MB is supported.
Page 96: Imaging
CHAPTER 3 CPU FUNCTIONS 3.4.2 Imaging The 4 GB CPU address space can be viewed as 256 images of a 16 MB physical address space. In other words, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address. The address space imaging is shown below.
Page 97: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0.
Page 98: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SC1, V850/SC2, and V850/SC3 reserve areas as shown below. Figure 3-6. Memory Map Single-chip mode Single-chip mode (external expansion mode) xxFFFFFFH On-chip peripheral On-chip peripheral 4 KB I/O area I/O area xxFFF000H xxFFEFFFH 28 KB Internal RAM area...
Page 99: Area
CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM/flash memory area An area of 1 MB maximum is reserved for the internal ROM/flash memory area. 512 KB are available for the addresses xx000000H to xx07FFFFH. Addresses xx080000H to xx0FFFFFH are an access-prohibited area Figure 3-7.
Page 100 CHAPTER 3 CPU FUNCTIONS Interrupt/exception table The V850/SC1, V850/SC2, and V850/SC3 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area.
Page 101: Internal Ram Area
CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area An area of 28 KB maximum is reserved for the internal RAM area. 24 KB are available for the addresses xxFF9000H to xxFFEFFFH. Addresses xxFF8000H to xxFF8FFFH are an access-prohibited area Figure 3-8. Internal RAM Area x x F F E F F F H Internal RAM x x F F 9 0 0 0 H...
Page 102: On-Chip Peripheral I/O Area
CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SC1, V850/SC2, and V850/SC3 are provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical on- chip peripheral I/O area.
Page 103: External Memory Area (When Expanded To 64 Kb, 256 Kb, Or 1 Mb)
CHAPTER 3 CPU FUNCTIONS (4) External memory The V850/SC1, V850/SC2, and V850/SC3 can use an area of up to 16 MB (xx100000H to xxFF7FFFH) for external memory accesses (in single-chip mode: external expansion). 64 KB, 256 KB, 1 MB, or 4 MB of physical external memory can be allocated when the external expansion mode is specified.
Page 104: External Memory Area (When Expanded To 4 Mb)
CHAPTER 3 CPU FUNCTIONS Figure 3-11. External Memory Area (When Expanded to 4 MB) xxFFFFFFH On-chip peripheral I/O Internal RAM xxFF7FFFH Image xxC00000H Physical external memory xxBFFFFFH 3FFFFFH xx800000H FCAN address area xx7FFFFFH 3FF800H 3FF7FFH External memory Image 000000H xx400000H xx3FFFFFH Image xx100000H...
Page 105: External Expansion Mode
CHAPTER 3 CPU FUNCTIONS 3.4.6 External expansion mode The V850/SC1, V850/SC2, and V850/SC3 allow external devices to be connected to the external memory space using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode using the memory expansion mode register (MM).
Page 106 CHAPTER 3 CPU FUNCTIONS (1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9 in the V850/SC1, V850/SC2, and V850/SC3. In the external expansion mode, an external device can be connected to an external memory area of up to 4 MB. However, the external device cannot be connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed).
Page 107 CHAPTER 3 CPU FUNCTIONS (2) Memory address output mode register (MAM) This register sets the mode of ports 3, 10, and 11 in the V850/SC1 and V850/SC2. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. The MAM register can be written in 8-bit units.
Page 108: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.7 Recommended use of address space The architecture of the V850/SC1, V850/SC2, and V850/SC3 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. Operand data can be accessed directly from an instruction in the ±32 KB above and below the address in this pointer register.
Page 109: Recommended Memory Map (Flash Memory Version)
CHAPTER 3 CPU FUNCTIONS Figure 3-13. Recommended Memory Map (Flash Memory Version) Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH Internal xxFFFFFFH Internal peripheral I/O FFFF8000H xxFFF400H FFFF7FFFH xxFFF3FFH External xxFFF000H memory xxFFEFFFH FF800000H FF7FFFFFH Internal xxFF9000H 01000000H xxFF8FFFH...
Page 110: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits Note √ √ FFFFF000H Port 0 √ √ FFFFF002H Port 1 √ √...
Page 111 CHAPTER 3 CPU FUNCTIONS (2/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF060H Data wait control register FFFFH √ FFFFF062H Bus cycle control register AAAAH Note 1 √...
Page 112 CHAPTER 3 CPU FUNCTIONS (3/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF0F6H Prescaler mode register 120 PRM120 √ √ FFFFF0F8H 16-bit timer mode control register 12 TMC12 √...
Page 113 CHAPTER 3 CPU FUNCTIONS (4/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ √ FFFFF140H Interrupt control register TMIC80 √ √ FFFFF142H Interrupt control register TMIC81 √ √ FFFFF144H Interrupt control register TMIC90...
Page 114 CHAPTER 3 CPU FUNCTIONS (5/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ √ FFFFF1A6H DMA channel control register 2 DCHC2 √ FFFFF1B0H DMA peripheral I/O address register 3 DIOA3 Undefined √...
Page 115 CHAPTER 3 CPU FUNCTIONS (6/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF23CH Baud rate generator mode control register 21 BRGMC √ √ FFFFF240H Clocked serial interface mode register 5 CSIM5 √...
Page 116 CHAPTER 3 CPU FUNCTIONS (7/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF28AH 16-bit counter 6 0000H √ FFFFF28CH 16-bit compare register 6 √ FFFFF28EH Timer clock select register 61 TCL61 √...
Page 117 CHAPTER 3 CPU FUNCTIONS (8/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF31EH Baud rate generator mode control register 10 BRGMC10 √ FFFFF320H Baud rate generator mode control register 01 BRGMC01 √...
Page 118 CHAPTER 3 CPU FUNCTIONS (9/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF390H 16-bit timer register 8 0000H √ FFFFF392H 16-bit capture/compare register 80 CR80 Note 1 √...
Page 119 CHAPTER 3 CPU FUNCTIONS (10/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits Note √ FFFFF3E8H IEBus control data register Note √ FFFFF3EAH IEBus telegraph length register Note √ FFFFF3ECH IEBus data register Note...
Page 120: Specific Registers
CHAPTER 3 CPU FUNCTIONS 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, the system status register (SYS) is notified.
Page 121 CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to erroneous program execution. This register can be written in 8-bit units. It becomes undefined in a read cycle. The occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
Page 122: Chapter 4 Clock Generation Function
CHAPTER 4 CLOCK GENERATION FUNCTION 4.1 General The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of system clock oscillators. (1) Main clock oscillator The V850/SC1 and V850/SC3 have an oscillation frequency of 4 to 20 MHz and the V850/SC2 4 to 18.87 MHz. Oscillation can be stopped by setting the STOP mode or by setting the processor clock control register (PCC).
Page 123: Configuration
CHAPTER 4 CLOCK GENERATION FUNCTION 4.2 Configuration Figure 4-1. Clock Generator Clock supplied to Subclock watch timer, etc. oscillator IDLE IDLE control CK2 to CK0 IDLE Main clock Prescaler HALT control oscillator CPU clock HALT Selector STP, control Clock supplied to Prescaler peripheral hardware CLKOUT...
Page 124: Control Registers
CHAPTER 4 CLOCK GENERATION FUNCTION 4.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8- or 1-bit units. After reset: Address: FFFFF074H <7>...
Page 125 CHAPTER 4 CLOCK GENERATION FUNCTION <3> MCK ← 1: Only when the main clock is stopped. (b) Example of subclock operation → → → → main clock operation setting <1> MCK ← 0: Main clock oscillation start <2> Insert waits using a program and wait until the main clock oscillation stabilization time elapses. <3>...
Page 126 CHAPTER 4 CLOCK GENERATION FUNCTION (3) Oscillation stabilization time select register (OSTS) This register can be read/written in 8-bit units. After reset: Address: FFFFF380H OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time Clock 20 MHz 18.87 MHz 16 MHz 3.3 ms 3.5 ms...
Page 127: Power Save Functions
CHAPTER 4 CLOCK GENERATION FUNCTION 4.4 Power Save Functions 4.4.1 General This product provides the following power saving functions. These modes can be combined and switched to suit the target application, thus enabling the effective implementation of low-power systems. (1) HALT mode In this mode, the clock oscillator continues to operate but the CPU operating clock is stopped.
Page 128: Halt Mode
CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.2 HALT mode (1) Settings and operating states In this mode, the clock oscillator continues to operate but the CPU operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain the operation of those functions. When HALT mode is set while the CPU is idle, it enables the system’s total power consumption to be reduced.
Page 129 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When CPU Operates on Main Clock When CPU Operates on Subclock When Subclock Does When Subclock When Main Clock When Main Clock Item Not Exist Exists Oscillation Continues Oscillation Is Stopped...
Page 130 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When CPU Operates on Main Clock When CPU Operates on Subclock When Subclock Does When Subclock Exists When Main Clock When Main Clock Item Not Exist Oscillation Continues Oscillation Is Stopped...
Page 131: Idle Mode
CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the subclock continues. When this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly.
Page 132 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings When Subclock Exists When Subclock Does Not Exist Item External bus interface Stopped External Operating interrupt INTP0 to INTP3, Operating request INTP7 to INTP9 INTP4 and INTP5 Stopped INTP6...
Page 133: Software Stop Mode
CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator supplying the internal main clock. The subclock oscillator continues operating and the internal subclock supply is continued. When the subclock oscillator is not used, if the FRC bit in the processor clock control register (PCC) is set (1), the subclock oscillator’s on-chip feedback resistor is cut.
Page 134 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-3. Operating Statuses in Software STOP Mode (1/2) Mode Settings When Subclock Exists When Subclock Does Not Exist Item Stopped ROM correction Stopped Clock generator Oscillation for main clock is stopped and oscillation for subclock continues Clock supply to CPU and on-chip peripheral functions is stopped 16-bit timer (TM0) Operates when INTWTNI is selected for the count...
Page 135 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-3. Operating Statuses in Software STOP Mode (2/2) Mode Settings When Subclock Exists When Subclock Does Not Exist Item DMA0 to DMA5 Stopped Port function Held External bus interface Stopped External Operating interrupt INTP0 to INTP3, Operating request INTP7 to INTP9...
Page 136: Oscillation Stabilization Time
CHAPTER 4 CLOCK GENERATION FUNCTION 4.5 Oscillation Stabilization Time The following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following cancellation of STOP mode. (1) Cancellation by non-maskable interrupt or by unmasked maskable interrupt request STOP mode is canceled by a non-maskable interrupt or an unmasked maskable interrupt request.
Page 137: Cautions On Power Save Function
CHAPTER 4 CLOCK GENERATION FUNCTION 4.6 Cautions on Power Save Function (1) When executing an instruction on the internal ROM To set the power save mode (IDLE or STOP mode) during execution of an instruction on the internal ROM, NOP instructions must be inserted as dummy instructions to execute the routine after the power save mode is released.
Page 138 CHAPTER 4 CLOCK GENERATION FUNCTION (2) When executing an instruction on the external ROM If the V850/SC1, V850/SC2, and V850/SC3 are used under the following conditions, a discrepancy occurs between the address indicated by the program counter (PC) and the address at which an instruction is actually read after the power save mode is released.
Page 139 CHAPTER 4 CLOCK GENERATION FUNCTION [Workaround program example] LDSR rX,5 ;Sets rX value to PSW ST.B r0,PRCMD[r0] ;Writes to PRCMD ST.B rD,PSC[r0] ;Sets PSC register LDSR rY,5 ;Returns PSW value ;6 or more NOP instructions ;Cancels PC discrepancy Remark It is assumed that rD (PSC setting value), rX (value written to PSW), and rY (value written back to PSW) have been set.
Page 140: Chapter 5 Port Functions
CHAPTER 5 PORT FUNCTIONS 5.1 Port Configuration The V850/SC1, V850/SC2, and V850/SC3 include 124 I/O port pins from ports 0 to 15 and 17 (12 port pins are input only). There are six pin I/O buffer power supplies; PORTV to PORTV , and ADCV , which are described below.
Page 141 CHAPTER 5 PORT FUNCTIONS (b) Other than µ µ µ µ PD70F3089Y Power Supply Corresponding Pins Usable Voltage Range 3.0 V ≤ PORTV ≤ 5.5 V Note 1 PORTV P40 to P47, P50 to P57, P60 to P65, P90 to P96, CLKOUT 3.0 V ≤...
Page 142: Port Pin Functions
CHAPTER 5 PORT FUNCTIONS 5.2 Port Pin Functions 5.2.1 Port 0 Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. When using P00 to P04 as the NMI or INTP0 to INTP3 pins, noise is eliminated by an analog noise eliminator. When using P05 to P07 as the INTP4/ADTRG, INTP5, and INTP6 pins, noise is eliminated by a digital noise eliminator.
Page 143 CHAPTER 5 PORT FUNCTIONS (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 0 mode register (PM0). In output mode, the values set to each bit are output to port 0 (P0). When using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for NMI requests).
Page 144 CHAPTER 5 PORT FUNCTIONS (3) Control registers (a) Port 0 mode register (PM0) PM0 can be read/written in 8- or 1-bit units. After reset: Address: FFFFF020H PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n Control of I/O mode (n = 0 to 7) Output mode Input mode (b) Rising edge specification register 0 (EGP0)
Page 145: Block Diagram Of P00 To P07
CHAPTER 5 PORT FUNCTIONS (c) Falling edge specification register 0 (EGN0) EGN0 can be read/written in 8- or 1-bit units. After reset: Address: FFFFF0C2H <7> <6> <5> <4> <3> <2> <1> <0> EGN0 EGN07 EGN06 EGN05 EGN04 EGN03 EGN02 EGN01 EGN00 EGN0n Control of falling edge detection (n = 0 to 7)
Page 146: Port 1
CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 Port 1 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Bits 0 and 2 are selectable as normal outputs or N-ch open-drain outputs. After reset: Address: FFFFF002H Control of output data (in output mode) (n = 0 to 7) Outputs 0 Outputs 1...
Page 147 CHAPTER 5 PORT FUNCTIONS (1) Function of P1 pins Port 1 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to port 1 (P1). The port 1 function register (PF1) can be used to specify whether P10 and P12 are normal outputs or N-ch open-drain outputs.
Page 148: Block Diagram Of P10 And P12
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 1) Figure 5-2. Block Diagram of P10 and P12 Selector PF1n PORT Output latch P-ch (P1n) P10/SI0/SDA0 P12/SCK0/SCL0 N-ch PM1n Alternate function Remarks 1. PF1: Port 1 function register PM1: Port 1 mode register Port 1 read signal Port 1 write signal 2.
Page 149: Block Diagram Of P11, P13 To P15, And P17
CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P11, P13 to P15, and P17 Selector PORT P11/SO0 Output latch P13/SI4/RXD0 (P1n) P14/SO4/TXD0 P15/SCK4/ASCK0 P17/TI5/TO5 PM1n Alternate function Remarks 1. PM1: Port 1 mode register Port 1 read signal Port 1 write signal 2.
Page 150: Block Diagram Of P16
CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P16 Selector PORT Output latch (P16) PM16 Remark PM1: Port 1 mode register Port 1 read signal Port 1 write signal User’s Manual U15109EJ3V0UD...
Page 151: Port 2
CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Bits 0 and 2 are selectable as normal outputs or N-ch open-drain outputs. After reset: Address: FFFFF004H Control of output data (in output mode) (n = 0 to 7) Outputs 0 Outputs 1...
Page 152 CHAPTER 5 PORT FUNCTIONS (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to port 2 (P2). Also, P20 and P22 are selectable as normal outputs or N-ch open-drain outputs using the port 2 function register (PF2).
Page 153: Block Diagram Of P20 And P22
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 2) Figure 5-5. Block Diagram of P20 and P22 Selector PF2n PORT Output latch P-ch (P2n) P20/SI2/SDA1 P22/SCK2/SCL1 N-ch PM2n Alternate function Remarks 1. PF2: Port 2 function register PM2: Port 2 mode register Port 2 read signal Port 2 write signal 2.
Page 154: Block Diagram Of P21 And P23 To P27
CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P21 and P23 to P27 Selector PORT P21/SO2 P23/TI90 Output latch P24/TI91 (P2n) P25/TO90 Note P26/IERX0 Note P25/IETX0 PM2n Alternate function Note Only for the V850/SC2 Remarks 1. PM2: Port 2 mode register Port 2 read signal WR: Port 2 write signal 2.
Page 155: Port 3
CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. When using P35 to P37 as the INTP7 to INTP9 pins, noise is eliminated by an analog eliminator. After reset: Address: FFFFF006H Control of output data (in output mode) (n = 0 to 7)
Page 156 CHAPTER 5 PORT FUNCTIONS (1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to port 3 (P3). When using this port in input mode, the pin statuses can be read by reading P3.
Page 157 CHAPTER 5 PORT FUNCTIONS (b) Rising edge specification register 1 (EGP1) EGP1 can be read/written in 8- or 1-bit units. After reset: Address: FFFFF0C4H <7> <6> <5> EGP1 EGP17 EGP16 EGP15 EGP1n Control of rising edge detection (n = 5 to 7) Interrupt request signal does not occur at rising edge Interrupt request signal occurs at rising edge Remark n = 5 to 7: Control of INTP7 to INTP9 pins...
Page 158: Block Diagram Of P30 To P37
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 3) Figure 5-7. Block Diagram of P30 to P37 Selector P30/TI6/TO6 PORT P31/TI80 P32/TI81 Output latch P33/TO8 (P3n) Note P34/TI71/A13 Note P35/INTP7/A14 Note P36/INTP8/A15 P37/INTP9 PM3n Alternate function Note Only for the V850/SC1 and V850/SC2 Remarks 1.
Page 159: Ports 4 And 5
CHAPTER 5 PORT FUNCTIONS 5.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF008H, FFFFF00AH (n = 4, 5) Control of output data (in output mode) (n = 4, 5, x = 0 to 7) Outputs 0 Outputs 1 Remark...
Page 160 CHAPTER 5 PORT FUNCTIONS (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via port 4 mode register (PM4) and port 5 mode register (PM5). In output mode, the values set to each bit are output to port 4 and port 5 (P4 and P5).
Page 161: Block Diagram Of P40 To P47 And P50 To P57
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (ports 4 and 5) Figure 5-8. Block Diagram of P40 to P47 and P50 to P57 Selector PORT Output latch Pmn/ADx (Pmn) PMmn Remarks 1. PMm: Port m mode register Port m read signal Port m write signal 2.
Page 162: Port 6
CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF00CH Control of output data (in output mode) (n = 0 to 5) Outputs 0 Outputs 1 Remark...
Page 163 CHAPTER 5 PORT FUNCTIONS (1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 6 mode register (PM6). In output mode, the values set to each bit are output to port 6 (P6). When using this port in input mode, the pin statuses can be read by reading P6.
Page 164: Block Diagram Of P60 To P65
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 6) Figure 5-9. Block Diagram of P60 to P65 Selector PORT Output latch P6n/Ax (P6n) PM6n Remarks 1. PM6: Port 6 mode register Port 6 read signal Port 6 write signal 2. n = 0 to 5 x = 16 to 21 User’s Manual U15109EJ3V0UD...
Page 165: Ports 7 And 8
CHAPTER 5 PORT FUNCTIONS 5.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8- or 1- bit units. After reset: Undefined Address: FFFFF00EH Pin level (n = 0 to 7) Read pin level of bit n...
Page 166: Block Diagram Of P70 To P77 And P80 To P83
CHAPTER 5 PORT FUNCTIONS (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading port 7 and port 8 (P7 and P8). Data cannot be written to P7 or P8. A software pull-up function is not implemented.
Page 167: Port 9
CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF012H Control of output data (in output mode) (n = 0 to 6) Outputs 0 Outputs 1 Remark...
Page 168 CHAPTER 5 PORT FUNCTIONS (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to port 9 (P9). When using this port in input mode, the pin statuses can be read by reading P9.
Page 169: Block Diagram Of P90 To P96
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 9) Figure 5-11. Block Diagram of P90 to P96 Selector Note P90/LBEN/WRL PORT P91/UBEN Note P92/R/W/WRH Output latch Note P93/DSTB/RD (P9n) P94/ASTB P95/HLDAK P96/HLDRQ PM9n Note Only for the V850/SC1 and V850/SC2 Remarks 1.
Page 170: Port 10
CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Pull-up resistors can be connected in 1-bit units (software pull-up function). When using P100 to P107 as the KR0 to KR7 pins, noise is eliminated by an analog noise eliminator. After reset: Address: FFFFF014H P107...
Page 171 CHAPTER 5 PORT FUNCTIONS (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to port 10 (P10). When using this port in input mode, the pin statuses can be read by reading P10.
Page 172: Block Diagram Of P100 To P107
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 10) Figure 5-12. Block Diagram of P100 to P107 PU10 PU10n P-ch Selector Note P100/KR0/TO7/A5 Note P101/KR1/TI70/A6 PORT Note P102/KR2/TI00/A7 Note P103/KR3/TI01/A8 Output latch Note (P10n) P104/KR4/TO0/A9 Note P105/KR5/TI10/A10 PM10 Note P106//KR6/TI11/A11 Note P107/KR7/TO1/A12 PM10n...
Page 173: Port 11
CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 11 Port 11 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. P11 can be read/written in 8- or 1-bit units. Turning on and off the wait function and setting use as the CANTX1, CANRX1, CANTX2, and CANRX2 pins can be performed via the port alternate-function control register (PAC) (CANTX2 and CANRX2 are available only for the µ...
Page 174 CHAPTER 5 PORT FUNCTIONS (1) Function of P11 pins Port 11 is an 8-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 11 mode register (PM11). In output mode, the values set to each bit are output to port 11 (P11). When using this port in input mode, the pin statuses can be read by reading P11.
Page 175 CHAPTER 5 PORT FUNCTIONS (b) Port alternate-function control register (PAC) PAC can be read/written in 8- or 1-bit units. After reset: Address: FFFFF040H <0> Note Note PAC117 PAC116 PAC115 PAC114 Control of wait function Wait function OFF Wait function ON PAC11n Control of port alternate function (n = 4 to 7) Port function...
Page 176: Block Diagram Of P110 And P114 To P117
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 11) Figure 5-13. Block Diagram of P110 and P114 to P117 Selector PORT Note 1 P110/WAIT/A Note 2 P114/CANTX1 Output latch Note 2 Selector P115/CANRX1 (P11n) Note 3 P116/CANTX2 Note 3 P117/CANRX2 PM11 PM11n PAC11m, WAC...
Page 177: Block Diagram Of P111 To P113
CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P111 to P113 Selector PORT Output latch Note P111/A2 (P11n) Note P113/A4 PM11 PM11n Alternate function Note Only for the V850/SC1 and V850/SC2 Remarks 1. PM11: Port 11 mode register Port 11 read signal Port 11 write signal 2.
Page 178: Port 12
CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 12 Port 12 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. P12 can be read/written in 8- or 1-bit units. When using this port as the SCK5, SI5, SO5, SCK6, SI6, and SO6 pins, set via port alternate-function control register 2 (PAC2).
Page 179 CHAPTER 5 PORT FUNCTIONS (1) Function of P12 pins Port 12 is an 8-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 12 mode register (PM12). In output mode, the values set to each bit are output to port 12 (P12). When using this port in input mode, the pin statuses can be read by reading P12.
Page 180: Block Diagram Of P120 To P125
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 12) Figure 5-15. Block Diagram of P120 to P125 Selector PORT Output latch Selector (P12n) PM12 PM12n PAC2 PAC12n Alternate function Remarks 1. PM12: Port 12 mode register Port 12 read signal Port 12 write signal PAC2: Port alternate-function control register 2 2.
Page 181: Block Diagram Of P126 And P127
CHAPTER 5 PORT FUNCTIONS Figure 5-16. Block Diagram of P126 and P127 Selector PORT Output latch P126/TO10 (P12n) P127/TO11 PM12 PM12n Alternate function Remarks 1. PM12: Port 12 mode register Port 12 read signal Port 12 write signal 2. n = 6, 7 User’s Manual U15109EJ3V0UD...
Page 182: Port 13
CHAPTER 5 PORT FUNCTIONS 5.2.12 Port 13 Port 13 is a 4-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF01AH P133 P132 P131 P130 P13n Control of output data (in output mode) (n = 0 to 3) Outputs 0 Outputs 1 Remark...
Page 183: Block Diagram Of P130 To P133
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 13) Figure 5-17. Block Diagram of P130 to P133 Selector PORT P130 P131 Output latch P132 (P13n) P133 PM13 PM13n Remarks 1. PM13: Port 13 mode register Port 13 read signal Port 13 write signal 2.
Page 184: Port 14
CHAPTER 5 PORT FUNCTIONS 5.2.13 Port 14 Port 14 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF01CH P147 P146 P145 P144 P143 P142 P141 P140 P14n Control of output data (in output mode) (n = 0 to 7) Outputs 0 Outputs 1 Remark...
Page 185 CHAPTER 5 PORT FUNCTIONS (1) Function of P14 pins Port 14 is an 8-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 14 mode register (PM14). In output mode, the values set to each bit are output to port 14 (P14). When using this port in input mode, the pin statuses can be read by reading P14.
Page 186: Block Diagram Of P140 To P147
CHAPTER 5 PORT FUNCTIONS Figure 5-18. Block Diagram of P140 to P147 Selector P140/SI3/RXD1 PORT P141/SO3/TXD1 P142/SCK3/ASCK1 Output latch P143/RXD2 (P14n) P144/TXD2 P145/ASCK2 P146/TI100 P147/TI101 PM14 PM14n Alternate function Remarks 1. PM14: Port 14 mode register Port 14 read signal Port 14 write signal 2.
Page 187: Port 15
CHAPTER 5 PORT FUNCTIONS 5.2.14 Port 15 Port 15 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF01EH P157 P156 P155 P154 P153 P152 P151 P150 P15n Control of output data (in output mode) (n = 0 to 7) Outputs 0 Outputs 1 Remark...
Page 188 CHAPTER 5 PORT FUNCTIONS (1) Function of P15 pins Port 15 is an 8-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 15 mode register (PM15). In output mode, the values set to each bit are output to port 15 (P15). When using this port in input mode, the pin statuses can be read by reading P15.
Page 189: Block Diagram Of P150 To P157
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 15) Figure 5-19. Block Diagram of P150 to P157 Selector P150/RXD3 PORT P151/TXD3 P152/ASCK3 Output latch P153/TI110 (P15n) P154/TI111 P155/TO12 P156/TI120 P157/TI121 PM15 PM15n Alternate function Remarks 1. PM15: Port 15 mode register Port 15 read signal Port 15 write signal 2.
Page 190: Port 17
CHAPTER 5 PORT FUNCTIONS 5.2.15 Port 17 Port 17 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF048H P176 P175 P174 P173 P172 P171 P170 P17n Control of output data (in output mode) (n = 0 to 6) Outputs 0 Outputs 1 Remark...
Page 191 CHAPTER 5 PORT FUNCTIONS (1) Function of P17 pins Port 17 is a 7-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 17 mode register (PM17). In output mode, the values set to each bit are output to port 17 (P17). When using this port in input mode, the pin statuses can be read by reading P17.
Page 192: Block Diagram Of P170 To P175
CHAPTER 5 PORT FUNCTIONS (3) Block diagram (port 17) Figure 5-20. Block Diagram of P170 to P175 Selector P170 PORT P171 P172 Output latch P173 (P17n) P174 P175 PM17 PM17n Remarks 1. PM17: Port 17 mode register Port 17 read signal Port 17 write signal 2.
Page 193: Block Diagram Of P176
CHAPTER 5 PORT FUNCTIONS Figure 5-21. Block Diagram of P176 Selector PORT Output latch (P176) P176/VM45 PM17 PM176 Alternate function Remark PM17: Port 17 mode register Port 17 read signal Port 17 write signal User’s Manual U15109EJ3V0UD...
Page 194: Setting When Port Pin Is Used For Alternate Function
CHAPTER 5 PORT FUNCTIONS 5.3 Setting When Port Pin Is Used for Alternate Function When a port pin is used for an alternate function, set the port n mode register (PM0 to PM6, PM9 to PM12, PM14, PM15, and PM17) and output latch as shown in Table 5-16 below. Table 5-16.
Page 195 CHAPTER 5 PORT FUNCTIONS Table 5-16. Setting When Port Pin Is Used for Alternate Function (2/6) Pin Name Alternate Function PMnx Bit of Pnx Bit of Other Bits PMn Register Pn Register (Register) Function Name Input PM20 = 1 Setting not needed –...
Page 196 CHAPTER 5 PORT FUNCTIONS Table 5-16. Setting When Port Pin Is Used for Alternate Function (3/6) Pin Name Alternate Function PMnx Bit of Pnx Bit of Other Bits PMn Register Pn Register (Register) Function Name P40 to P47 AD0 to AD7 Setting not needed Setting not needed Refer to 3.4.6 (1) (MM)
Page 197 CHAPTER 5 PORT FUNCTIONS Table 5-16. Setting When Port Pin Is Used for Alternate Function (4/6) Pin Name Alternate Function PMnx Bit of Pnx Bit of Other Bits PMn Register Pn Register (Register) Function Name P103 Input PM103 = 1 Setting not needed for P103 –...
Page 198 CHAPTER 5 PORT FUNCTIONS Table 5-16. Setting When Port Pin Is Used for Alternate Function (5/6) Pin Name Alternate Function PMnx Bit of Pnx Bit of Other Bits PMn Register Pn Register (Register) Function Name Note P116 CANTX2 Output PM116 = 0 P116 = 0 PAC116 = 1 (PAC) Note...
Page 199 CHAPTER 5 PORT FUNCTIONS Table 5-16. Setting When Port Pin Is Used for Alternate Function (6/6) Pin Name Alternate Function PMnx Bit of Pnx Bit of Other Bits PMn Register Pn Register (Register) Function Name P152 ASCK3 Input PM152 = 1 Setting not needed –...
Page 200: Operation Of Port Function
CHAPTER 5 PORT FUNCTIONS 5.4 Operation of Port Function The operation of a port differs depending on whether the port is in the input or output mode, as described below. 5.4.1 Writing data to I/O port (1) In output mode A value can be written to the output latch by using a transfer instruction.
Page 201: Chapter 6 Bus Control Function
CHAPTER 6 BUS CONTROL FUNCTION The V850/SC1, V850/SC2, and V850/SC3 are provided with an external bus interface function by which external memories, such as ROM and RAM, and I/O can be connected. 6.1 Features • Address bus (separate output possible only for the V850/SC1 and V850/SC2) •...
Page 202: Bus Control Pins And Control Register
CHAPTER 6 BUS CONTROL FUNCTION 6.2 Bus Control Pins and Control Register 6.2.1 Bus control pins The following pins are used for interfacing to external devices. Table 6-1. Bus Control Pins External Bus Interface Function Corresponding Port (Pins) Address/data bus (AD0 to AD7) Port 4 (P40 to P47) Address/data bus (AD8 to AD15) Port 5 (P50 to P57)
Page 203: Control Register
CHAPTER 6 BUS CONTROL FUNCTION 6.2.2 Control register (1) System control register (SYC) (V850/SC1, V850/SC2) This register switches control signals for the bus interface. The system control register can be read/written in 8- or 1-bit units. After reset: 00H Address: FFFFF064H Symbol <0>...
Page 204: Bus Width
CHAPTER 6 BUS CONTROL FUNCTION 6.3.2 Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types: access to even addresses and access to odd addresses. Figure 6-1.
Page 205: Memory Block Function
CHAPTER 6 BUS CONTROL FUNCTION 6.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 6-4.
Page 206: Wait Function
CHAPTER 6 BUS CONTROL FUNCTION 6.5 Wait Function 6.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. The number of wait states can be programmed by using the data wait control register (DWC).
Page 207: External Wait Function
CHAPTER 6 BUS CONTROL FUNCTION 6.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to the programmable wait.
Page 208: Idle State Insertion Function
CHAPTER 6 BUS CONTROL FUNCTION 6.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle following continuous bus cycles starts after one idle state.
Page 209: Bus Hold Function
CHAPTER 6 BUS CONTROL FUNCTION 6.7 Bus Hold Function 6.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, Note the external address/data bus and strobe pins go into a high-impedance state , and the bus is released (bus hold...
Page 210: Bus Hold Procedure
CHAPTER 6 BUS CONTROL FUNCTION 6.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 6-7. Bus Hold Procedure <1> HLDRQ = 0 acknowledged Normal status <2> All bus cycle start requests pending <3> End of current bus cycle <4>...
Page 211: Bus Timing
CHAPTER 6 BUS CONTROL FUNCTION 6.8 Bus Timing The V850/SC1, V850/SC2, and V850/SC3 can execute read/write control for an external device using the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC) (see 6.2.2 (1) System control register (SYC) (V850/SC1, V850/SC2)).
Page 212 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (2/4) (b) 1 wait CLKOUT (output) Address A16 to A21 (output) Note Address A1 to A15 (output) AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) Note Note , WRL (output) Note DSTB, RD...
Page 213 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (3/4) (c) 0 waits, idle state CLKOUT (output) Address A16 to A21 (output) Address Note A1 to A15 (output) AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) Note Note , WRL (output) Note...
Page 214 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (4/4) (d) 1 wait, idle state CLKOUT (output) Address A16 to A21 (output) Note Address A1 to A15 (output) AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) Note Note , WRL (output) Note...
Page 215 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-9. Memory Write (1/2) (a) 0 waits CLKOUT (output) A16 to A21 (output) Address Note 1 A1 to A15 (output) Address Note 2 Address Data AD0 to AD15 (I/O) ASTB (output) R/W (output) Note 1 (output) DSTB (output) Note 1...
Page 216 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-9. Memory Write (2/2) (b) 1 wait CLKOUT (output) A16 to A21 (output) Address Note 1 A1 to A15 (output) Address Note 2 Address Data AD0 to AD15 (I/O) ASTB (output) R/W (output) Note 1 (output) DSTB (output) Note 1...
Page 217 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-10. Bus Hold Timing CLKOUT (output) HLDRQ (input) Note 1 HLDAK (output) Address A16 to A21 (output) Address Note 2 A1 to A15 (output) Address Address AD0 to AD15 (I/O) Address Data Undefined Address ASTB (output) Note 3 R/W (output)
Page 218: Bus Priority
CHAPTER 6 BUS CONTROL FUNCTION 6.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order.
Page 219: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.1 Outline The V850/SC1, V850/SC2, and V850/SC3 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 49 to 56 sources.
Page 220 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (1/3) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register − − − Reset Interrupt RESET Reset input 0000H 00000000H Undefined − −...
Page 221 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (2/3) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register Maskable Interrupt INTTM6/ TM6 compare match/ TM6/pin 0200H 00000200H nextPC TMIC6 Note 1 INTP9 OVF/INTP9 pin INTSR0/...
Page 222 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (3/3) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register Maskable Interrupt INTTM101 TM10 and CR101 match/ TM10 03A0H 000003A0H nextPC TMIC101 TI100 pin valid edge INTTM110 TM11 and CR110 match/...
Page 223: Non-Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupts Non-maskable interrupts are acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are available in the V850/SC1, V850/SC2, and V850/SC3. •...
Page 224: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes the exception code (0010H, 0020H) to the higher halfword (FECC) of ECR.
Page 225 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Requests (a) If a new NMI request is generated while an NMI service routine is being executed: Main routine (PSW. NP = 1) NMI request NMI request NMI request held pending regardless of the NP bit of PSW Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is being executed: Main routine...
Page 226: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 227: Np Flag
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 228: Edge Detection Function Of Nmi Pin
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, neither rising nor falling edge detected. Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of non-maskable interrupts (NMI).
Page 229: Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SC1, V850/SC2, and V850/SC3 have 49 to 56 maskable interrupt sources (refer to 7.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 230 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-5. Maskable Interrupt Servicing INT input INTC acknowledged Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request...
Page 231: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore To restore execution from the maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 232: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850/SC1, V850/SC2, and V850/SC3 provide a multiple interrupt service in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxPRn).
Page 233 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Interrupt Nesting Process (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority (level 3) (level 2) of b is higher than that of a and interrupts are enabled. Servicing of c Interrupt request c Interrupt request d...
Page 234 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Interrupt Nesting Process (2/2) Main routine Servicing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 235: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-8. Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) Servicing of interrupt request b • Interrupt request b and c are Note 2 Interrupt request c (level 1) acknowledged first according to their...
Page 236 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: 47H Address: FFFFF100H to FFFFF172H Symbol <7> <6> xxICn xxIFn xxMKn xxPRn2 xxPRn1 xxPRn0 Note xxIFn Interrupt request flag Interrupt request not generated Interrupt request generated xxMKn Interrupt mask flag Enables interrupt servicing Disables interrupt servicing (pending) xxPRn2 xxPRn1...
Page 237 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The addresses and bits of the interrupt control registers are as follows. Table 7-2. Interrupt Control Registers (xxICn) (1/2) Address Register <7> <6> FFFFF100H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF102H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF104H...
Page 238 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Interrupt Control Registers (xxICn) (2/2) Address Register <7> <6> FFFFF14CH DMAIC3 DMAIF3 DMAMK3 DMAPR32 DMAPR31 DMAPR30 FFFFF14EH DMAIC4 DMAIF4 DMAMK4 DMAPR42 DMAPR41 DMAPR40 FFFFF150H DMAIC5 DMAIF5 DMAMK5 DMAPR52 DMAPR51 DMAPR50 Note FFFFF152H CANIC4 CANIF4 CANMK4 CANPR42...
Page 239: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently requesting acknowledgement. When the interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced.
Page 240: Watchdog Timer Mode Register (Wdtm)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Watchdog timer mode register (WDTM) This register can be read/written in 8- or 1-bit units (for details, refer to CHAPTER 10 WATCHDOG TIMER). After reset: 00H Address: FFFFF384H Symbol <7> WDTM WDTM4 WDTM3 Watchdog timer operation control Count operation stopped Count started after clearing WDTM4...
Page 241 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Elimination of noise from INTP6 pin A digital noise eliminator is provided on chip. The sampling clock for digital sampling can be selected from among f /64, f /128, f /256, f /512, f /1024, and f .
Page 242: Edge Detection Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.9 Edge detection function Valid edges of the INTP0 to INTP9 pins can be selected for each pin from the following four types. • Rising edge • Falling edge • Both rising and falling edges •...
Page 243: Software Exceptions
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Series Architecture User’s Manual. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine:...
Page 244: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore To restore or return execution from a software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 245: Ep Flag
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 EP flag The EP flag in the PSW is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 7-12. EP Flag (EP) After reset: 00000020H Symbol NP EP ID SAT CY OV Exception processing...
Page 246: Exception Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850/SC1, V850/SC2, and V850/SC3, an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap.
Page 247: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 248: Priority Control
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Priority Control 7.6.1 Priorities of interrupts and exceptions Table 7-3. Priorities of Interrupts and Exceptions RESET TRAP ILGOP RESET × ← ← ← × ↑ ← ← × ↑ ↑ ← TRAP × ↑ ↑...
Page 249: Multiple Interrupt Servicing
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6.2 Multiple interrupt servicing Multiple interrupt servicing is a function that allows the nesting of interrupts. If a higher priority interrupt is generated and acknowledged, it will be allowed to stop an interrupt service routine currently in progress. Execution of the original routine will resume once the higher priority interrupt routine is completed.
Page 250 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request in multiple interrupt servicing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request.
Page 251: Response Time
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Response Time The following table describes the interrupt response time (from interrupt request generation to start of interrupt servicing). Figure 7-16. Pipeline Operation at Interrupt Request Acknowledgement 7 to 14 system clocks 4 system clocks System clock Interrupt request Instruction 1...
Page 252: Periods In Which Interrupts Are Not Acknowledged
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which Interrupts Are Not Acknowledged Interrupts are acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. Interrupt request non-sample instruction •...
Page 253 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION [Program processing example] ;(MK flag = 0) ;← Interrupt request generated (IF flag = 1) ;EI instruction executed ;1 system clock ;1 system clock Note ;1 system clock ;1 system clock ;3 system clocks (branched to LP1 routine) ;LP1 routine ;After EI instruction executed, executed at the 8th clock by NOP x 4 and JR instructions...
Page 254: Bit Manipulation Instruction Of Interrupt Control Register On Dma Transfer
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-17. Pipeline Flow and Interrupt Request Generation Timing (a) When DI instruction is executed at 8th system clock after EI instruction execution (interrupt request is acknowledged) ei signal intrq signal intrq signal generated (b) When DI instruction is executed at 7th system clock after EI instruction execution (interrupt request is not acknowledged) ei signal intrq signal...
Page 255: Key Interrupt Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.10 Key Interrupt Function A key interrupt can be generated by inputting a falling edge to key input pins (KR0 to KR7) by setting the key return mode register (KRM). The key return mode register (KRM) includes 5 bits. The KRM0 bit controls the KR0 to KR3 signals in 4-bit units and the KRM4 to KRM7 bits control corresponding signals from KR4 to KR7 (arbitrary setting from 4 to 8 bits is possible).
Page 256 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-18. Block Diagram of Key Return INTKR KRM7 KRM6 KRM5 KRM4 KRM0 Key return mode register (KRM) User’s Manual U15109EJ3V0UD...
Page 257: Chapter 8 Timer/Counter Function
CHAPTER 8 TIMER/COUNTER FUNCTION 8.1 16-Bit Timer (TM0, TM1, TM7 to TM12) 8.1.1 Outline • 16-bit capture/compare registers: 2 (CRn0, CRn1) • Independent capture/trigger inputs: 2 (TIn0, TIn1) • Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) • Event input (shared with TIn0) via digital noise eliminator and support of edge specifications •...
Page 258 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-1. Block Diagram of TM0, TM1, and TM7 to TM12 Internal bus Capture/compare control register n (CRCn) CRCn2 CRCn1 CRCn0 Selector INTTMn0 16-bit capture/compare Noise Selector TIn1 register n0 (CRn0) eliminator Match Note Count clock Clear Output 16-bit timer register (TMn)
Page 259: Configuration
CHAPTER 8 TIMER/COUNTER FUNCTION 8.1.3 Configuration Timers 0, 1, and 7 to 12 include the following hardware. Table 8-1. Configuration of Timers 0, 1, and 7 to 12 Item Configuration 16 bits × 8 (TM0, TM1, TM7 to TM12) Timer registers Capture/compare registers: 16 bits ×...
Page 260 CHAPTER 8 TIMER/COUNTER FUNCTION (2) Capture/compare register n0 (CR00, CR10, CR70 to CR120) CRn0 is a 16-bit register that functions as both a capture register and a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register (n = 0, 1, 7 to 12).
Page 261 CHAPTER 8 TIMER/COUNTER FUNCTION (3) Capture/compare register n1 (CR01, CR11, CR71 to CR121) This is a 16-bit register that can be used as both a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRCn2) of the CRCn register (n = 0, 1, 7 to 12). (a) When using CRn1 as compare register The value set to CRn1 is continually compared with the count value of TMn.
Page 262: Timer 0, 1, 7 To 12 Control Registers
CHAPTER 8 TIMER/COUNTER FUNCTION 8.1.4 Timer 0, 1, 7 to 12 control registers Timers 0, 1, and 7 to 12 are controlled by the following registers. • 16-bit timer mode control register n (TMCn) • Capture/compare control register n (CRCn) •...
Page 263 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H Address: TMC0: FFFFF208H TMC1: FFFFF218H TMC7: FFFFF3A8H TMC8: FFFFF398H TMC9: FFFFF3B8H TMC10: FFFFF0D8H TMC11: FFFFF0E8H TMC12: FFFFF0F8H <0> TMCn TMCn3 TMCn2 TMCn1 OVFn (n = 0, 1, 7 to 12) TMCn3 TMCn2 TMCn1 Selects operation mode Selects TOn output Generation of interrupt...
Page 264 CHAPTER 8 TIMER/COUNTER FUNCTION (2) Capture/compare control registers 0, 1, 7 to 12 (CRC0, CRC1, CRC7 to CRC12) CRCn controls the operation of capture/compare register n (CRn0 and CRn1). CRCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0, CRC1, and CRC7 to CRC12 to 00H.
Page 265 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H R/W Address: TOC0: FFFFF20CH TOC1: FFFFF21CH TOC7: FFFFF3ACH TOC8: FFFFF39CH TOC9: FFFFF3BCH TOC10: FFFFF0DCH TOC11: FFFFF0ECH TOC12: FFFFF0FCH <6> <5> <3> <2> <0> TOCn OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn (n = 0, 1, 7 to 12) OSPTn Controls output trigger of one-shot pulse by software No one-shot pulse trigger...
Page 266 CHAPTER 8 TIMER/COUNTER FUNCTION (4) Prescaler mode registers 00, 01 (PRM00, PRM01) PRM0n selects the count clock of the 16-bit timer (TM0) and the valid edges of the TI00 and TI01 inputs. PRM00 and PRM01 are set by an 8-bit memory manipulation instruction. RESET input clears PRM00 and PRM01 to 00H.
Page 267 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TI00 as the count clock, do not specify the valid edge of TI00 to clear and start the timer and as a capture trigger. 2. Before setting data to PRM00 and PRM01, always stop the timer operation. 3.
Page 268 CHAPTER 8 TIMER/COUNTER FUNCTION (5) Prescaler mode registers 10, 11, 70, 71 (PRM10, PRM11, PRM70, PRM71) PRM1n selects the count clock of the 16-bit timer (TM1, TM7) and the valid edge of the TIn0 and TIn1 inputs. PRMn0 and PRMn1 are set by an 8-bit memory manipulation instruction (n = 1, 7). RESET input clears PRMn0 and PRMn1 to 00H.
Page 269 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TIn0 as the count clock, do not specify the valid edge of TIn0 to clear and start the timer and as a capture trigger. 2. Before setting data to PRMn0 and PRMn1, always stop the timer operation. 3.
Page 270 CHAPTER 8 TIMER/COUNTER FUNCTION (6) Prescaler mode registers 80, 81, 100, 101, 120, 121 (PRM80, PRM81, PRM100, PRM101, PRM120, PRM121) PRM1n selects the count clock of the 16-bit timer (TM8, TM10, TM12) and the valid edge of the TIn0 and TIn1 inputs.
Page 271 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TIn0 as the count clock, do not specify the valid edge of TIn0 to clear and start the timer and as a capture trigger. 2. Before setting data to PRMn0 and PRMn1, always stop the timer operation. 3.
Page 272 CHAPTER 8 TIMER/COUNTER FUNCTION (7) Prescaler mode registers 90, 91, 110, 111 (PRM90, PRM91, PRM110, PRM111) PRM1n selects the count clock of the 16-bit timer (TM9, TM11) and the valid edge of the TIn0 and TIn1 inputs. PRMn0 and PRMn1 are set by an 8-bit memory manipulation instruction (n = 9, 11). RESET input clears PRMn0 and PRMn1 to 00H.
Page 273 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TIn0 as the count clock, do not specify the valid edge of TIn0 to clear and start the timer and as a capture trigger. 2. Before setting data to PRMn0 and PRMn1, always stop the timer operation. 3.
Page 274: 16-Bit Timer (Tm0, Tm1, Tm7 To Tm12) Operation
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2 16-Bit Timer (TM0, TM1, TM7 to TM12) Operation 8.2.1 Operation as interval timer TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 8-2 (n = 0, 1). In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value preset to 16- bit capture/compare register n0 (CRn0).
Page 275 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-3. Configuration of Interval Timer ELW FDSWXUHFRPSDUH UHJLVWHU Q &5Q ,1770Q &RXQW FORFN 490 6HOHFWRU ELW WLPHU UHJLVWHU Q 70Q 29)Q 1RLVH 7,Q HOLPLQDWRU &OHDU FLUFXLW Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
Page 276: Ppg Output Operation
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 8-5. The PPG output function outputs a square-wave from the TOn pin with a cycle specified by the count value preset to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value preset to 16-bit capture/compare register n1 (CRn1).
Page 277 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-6. Configuration of PPG Output 16-bit capture/compare register n0 (CRn0) Clear Note Count clock 16-bit timer register n (TMn) circuit Noise TIn0 eliminator 16-bit capture/compare register n1 (CRn1) Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
Page 278: Pulse Width Measurement
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin.
Page 279 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-9. Configuration for Pulse Width Measurement with Free-Running Counter &RXQW FORFN 490 29)Q 6HOHFWRU ELW WLPHU UHJLVWHU Q 70Q ELW FDSWXUHFRPSDUH UHJLVWHU Q 7,Q &5Q ,1770Q ,QWHUQDO EXV Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
Page 280 CHAPTER 8 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 8-11). When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set.
Page 281 CHAPTER 8 TIMER/COUNTER FUNCTION • Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 8-12. CRn1 Capture Operation with Rising Edge Specified &RXQW FORFN 1 − 1 − 1 −...
Page 282 CHAPTER 8 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 8-14), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
Page 283 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) &RXQW FORFN 70Q FRXQW + + D 0 + 1 D 1 + 1 ))))+ + D 2 + 1 YDOXH 7,Q SLQ LQSXW 9DOXH ORDGHG...
Page 284 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin.
Page 285: Operation As External Event Counter
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n0 (PRMn0) is input, TMn is incremented.
Page 286 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-19. Configuration of External Event Counter ELW FDSWXUHFRPSDUH UHJLVWHU Q &5Q 0DWFK ,1770Q &OHDU &RXQW FORFN 490 6HOHFWRU 29)Q ELW WLPHUFRXQWHU Q 70Q 1RLVH HOLPLQDWRU ELW FDSWXUHFRPSDUH 9DOLG HGJH RI 7,Q UHJLVWHU Q &5Q ,QWHUQDO EXV Note The count clock is set by the PRMn0 and PRMn1 registers.
Page 287: Operation As Square-Wave Output
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.5 Operation as square-wave output TMn can be used to output a square-wave with any frequency at an interval specified by the count value preset to 16-bit capture/compare register n0 (CRn0). By setting bits 0 (TOEn) and 1 (TOCn1) of 16-bit timer output control register n (TOCn) to 1, the output status of the TOn pin is inverted at an interval specified by the count value preset to CRn1.
Page 288: Operation As One-Shot Pulse Output
CHAPTER 8 TIMER/COUNTER FUNCTION Remarks 1. 0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with the square-wave output function. For details, refer to 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12) and (2) Capture/compare control registers 0, 1, 7 to 12 (CRC0, CRC1, CRC7 to CRC12).
Page 289 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-23. Control Register Settings for One-Shot Pulse Output via Software Trigger (a) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12) TMCn3 TMCn2 TMCn1 OVFn TMCn Free-running mode (b) Capture/compare control registers 0, 1, 7 to 12 (CRC0, CRC1, CRC7 to CRC12) CRCn2 CRCn1 CRCn0...
Page 290 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-24. Timing of One-Shot Pulse Output Operation via Software Trigger 6HWV &+ WR 70&Q 70Q FRXQW VWDUWV &RXQW FORFN 70Q FRXQW + + + 1 − 0 − YDOXH CRn1 set value &5Q VHW YDOXH 2637Q ,1770Q...
Page 291 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-25. Control Register Settings for One-Shot Pulse Output via External Trigger (a) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin.
Page 292 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-26. Timing of One-Shot Pulse Output Operation via External Trigger (with Rising Edge Specified) 6HWV + WR 70&Q 70Q FRXQW VWDUWV &RXQW FORFN 70Q FRXQW + + + 0 − 0 − YDOXH 9DOXH WR VHW &5Q 9DOXH WR VHW &5Q...
Page 293: Cautions
CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 8-27.
Page 294 CHAPTER 8 TIMER/COUNTER FUNCTION (4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1 performs the capture operation, but this capture value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge.
Page 295 CHAPTER 8 TIMER/COUNTER FUNCTION (7) Operation of OVFn flag (a) OVFn flag set The OVFn flag is set to 1 in the following case in addition to when TMn register overflows: Selection of mode in which TM0 is cleared and started on a match between TMn and CRn0. ↓...
Page 296 CHAPTER 8 TIMER/COUNTER FUNCTION (9) Timer operation (a) CRn1 capture Even if 16-bit timer register n (TMn) is read, a capture to 16-bit capture/compare register n1 (CRn1) is not performed. (b) Acknowledgement of TIn0 and TIn1 pins When the timer is stopped, input signals to the TIn0 and TIn1 pins are not acknowledged, regardless of the CPU operation.
Page 297 CHAPTER 8 TIMER/COUNTER FUNCTION (12) Edge detection (a) When the TIn0 or TIn1 pin is high level immediately after a system reset When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (TMn) is then enabled, the rising edge will be detected immediately.
Page 298: 16-Bit Timer (Tm5, Tm6)
CHAPTER 8 TIMER/COUNTER FUNCTION 8.3 16-Bit Timer (TM5, TM6) 8.3.1 Functions TM5 and TM6 have the following functions. • PWM output with 16-bit resolution • Interval timer with 16-bit resolution • External event counter with 16-bit resolution • Square-wave output with 16-bit resolution Figure 8-31.
Page 299: Configuration
CHAPTER 8 TIMER/COUNTER FUNCTION 8.3.2 Configuration Timer n includes the following hardware. Table 8-5. Configuration of Timers 5 and 6 Item Configuration Timer registers 16-bit counters 5, 6 (TM5, TM6) Registers 16-bit compare registers 5, 6 (CR5, CR6) Timer outputs TO5, TO6 Control registers Timer clock select registers 50, 51, 60, and 61 (TCL50, TCL51, TCL60, and TCL61)
Page 300: Timer N Control Registers
CHAPTER 8 TIMER/COUNTER FUNCTION 8.3.3 Timer n control registers Timer n is controlled by the following registers. • Timer clock select registers n0, n1 (TCLn0, TCLn1) • 16-bit timer mode control register n (TMCn) (1) Timer clock select registers 50, 51, 60, 61 (TCL50, TCL51, TCL60, TCL61) These registers set the count clock of timer n.
Page 301 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H Address: FFFFF28EH TCL61 TCL603 After reset: 00H Address: FFFFF284H TCL60 TCL602 TCL601 TCL600 TCL603 TCL602 TCL601 TCL600 Count clock selection Count clock 20 MHz 18.87 MHz 16 MHz − − − TI6 falling edge −...
Page 302 CHAPTER 8 TIMER/COUNTER FUNCTION (2) 16-bit timer mode control registers 50, 60 (TMC50, TMC60) The TMCn0 register makes the following five settings. (1) Controls the counting by 16-bit counter n (TMn) (2) Selects the operating mode of 16-bit counter n (TMn) (3) Sets the state of the timer output flip-flop (4) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode (5) Controls timer output...
Page 303 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: Address: TMC50 FFFFF336H TMC60 FFFFF286H <7> <3> <2> <0> TMCn0 TMCn06 TCEn0 LVSn0 LVRn0 TMCn01 TOEn0 (n = 5, 6) TCEn0 TMn count operation control Counting is disabled after the counter is cleared to 0 (prescaler disabled) Start count operation TMCn06 TMn operating mode selection...
Page 304: 16-Bit Timer (Tm5, Tm6) Operation
CHAPTER 8 TIMER/COUNTER FUNCTION 8.4 16-Bit Timer (TM5, TM6) Operation 8.4.1 Operation as an interval timer TMn operates as an interval timer that repeatedly generates interrupts at the time interval specified by the count value preset to 16-bit compare register n (CRn). When the count value of 16-bit counter n (TMn) matches the set value of CRn, the value of TMn is cleared to 0, and the timer continues counting.
Page 305 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-32. Timing of Interval Timer Operation (2/2) When CRn = 0000H &RXQW FORFN 70Q 0000 H 0000 H 0000 H 0000 H 0000 H &5Q 7&(Q ,1770Q ,QWHUYDO WLPH Remark n = 5, 6 When CRn = FFFFH &RXQW FORFN 0001H FFFEH...
Page 306: Operation As External Event Counter
CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIn. Each time the valid edge specified by timer clock select registers n0 and n1 (TCLn0, TCLn1) is input, TMn is incremented.
Page 307: Operation As Square-Wave Output
CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.3 Operation as square-wave output A square-wave with any frequency is output at the interval preset to 16-bit compare register n (CRn). By setting bit 0 (TOEn0) of 16-bit timer mode control register n0 (TMCn0) to 1, the output status of TOn is inverted at an interval specified by the count value preset to CRn.
Page 308: Operation As 16-Bit Pwm Output
CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.4 Operation as 16-bit PWM output By setting bit 6 (TMCn6) of 16-bit timer mode control register n0 (TMCn0) to 1, the timer operates as a PWM output. Pulses with the duty ratio determined by the value set to 16-bit compare register n (CRn) are output from TOn. Set the width of the active level of the PWM pulse to CRn.
Page 309 CHAPTER 8 TIMER/COUNTER FUNCTION (a) Basic operation of PWM output Figure 8-35. Timing of PWM Output Basic operation (active level = H) &RXQW FORFN + 0001H FFFFH 0000H 0001H 0002H FFFFH 0000H 0001H 0002H 0 + &5Q 7&(Q ,1770Q $FWLYH OHYHO ,QDFWLYH OHYHO $FWLYH OHYHO When CRn = 0...
Page 310: Cautions
CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.5 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit counter n (TMn) is started asynchronously to the count pulse. Figure 8-36.
Page 311: Chapter 9 Watch Timer Function
CHAPTER 9 WATCH TIMER FUNCTION 9.1 Function The watch timer has the following functions. • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 9-1. Block Diagram of Watch Timer Clear 5-bit counter INTWTN...
Page 312: Configuration
CHAPTER 9 WATCH TIMER FUNCTION (1) Watch timer The watch timer generates an interrupt request (INTWTN) at time intervals of 0.5 or 0.25 second by using the main clock or subclock. (2) Interval timer The watch timer generates an interrupt request (INTWTNI) at time intervals specified in advance. Table 9-1.
Page 313: Watch Timer Control Register
CHAPTER 9 WATCH TIMER FUNCTION 9.3 Watch Timer Control Register The watch timer mode control register (WTNM), watch timer high-speed clock select register (WTNHC), and watch timer clock select register (WTNCS) control the watch timer. The watch timer should be operated after setting the count clock and interval time.
Page 314 CHAPTER 9 WATCH TIMER FUNCTION (2) Watch timer high-speed clock select register (WTNHC) This register selects the count clock of the watch timer. The count clock is determined using WTNM7 bit of WTNM register in combination with WTNCS1 and WTNCS0 bits of the watch timer clock select register (WTNCS).
Page 315: Operation
CHAPTER 9 WATCH TIMER FUNCTION 9.4 Operation 9.4.1 Operation as watch timer The watch timer operates with time intervals of 0.5 second with the subclock (32.768 kHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTNM0) and 1 (WTNM1) of the watch timer mode control register (WTNM) are set to 1.
Page 316: Operation As Interval Timer
CHAPTER 9 WATCH TIMER FUNCTION 9.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. The interval time can be selected by bits 4 to 6 (WTNM4 to WTNM6) of the watch timer mode control register (WTNM).
Page 317: Cautions
CHAPTER 9 WATCH TIMER FUNCTION 9.4.3 Cautions It takes some time to generate the first watch timer interrupt request (INTWTN) after operation is enabled (WTNM1 and WTNM0 bits of WTNM register = 1). Figure 9-3. Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s) ×...
Page 318: Watchdog Timer Function
CHAPTER 10 WATCHDOG TIMER FUNCTION 10.1 Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode.
Page 319 CHAPTER 10 WATCHDOG TIMER FUNCTION (1) Watchdog timer mode This mode detects an inadvertent program loop. When a loop is detected, a non-maskable interrupt can be generated. Table 10-1. Loop Detection Time of Watchdog Timer Clock Loop Detection Time = 20 MHz = 18.87 MHz = 16 MHz 3.3 ms...
Page 320: Configuration
CHAPTER 10 WATCHDOG TIMER FUNCTION 10.2 Configuration The watchdog timer includes the following hardware. Table 10-3. Watchdog Timer Configuration Item Configuration Control registers Oscillation stabilization time select register (OSTS) Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) 10.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following registers.
Page 321 CHAPTER 10 WATCHDOG TIMER FUNCTION (2) Watchdog timer clock select register (WDCS) This register selects the overflow times of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. After reset: 00H Address: FFFFF382H WDCS...
Page 322 CHAPTER 10 WATCHDOG TIMER FUNCTION (3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, enables and disables counting, and generates internal reset signals. WDTM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets WDTM to 00H.
Page 323: Operation
CHAPTER 10 WATCHDOG TIMER FUNCTION 10.4 Operation 10.4.1 Operation as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect inadvertent program looping. Setting bit 7 (RUN) of WDTM to 1 starts the count. After counting starts, if RUN is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again.
Page 324: Operation As Interval Timer
CHAPTER 10 WATCHDOG TIMER FUNCTION 10.4.2 Operation as interval timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 0 to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flags (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated.
Page 325: Standby Function Control Register
CHAPTER 10 WATCHDOG TIMER FUNCTION 10.5 Standby Function Control Register (1) Oscillation stabilization time select register (OSTS) The wait time from when the stop mode is cancelled until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction.
Page 326: Chapter 11 Serial Interface Function
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.1 Overview The V850/SC1, V850/SC2, and V850/SC3 incorporate the following serial interfaces. • Note Channel 0: 3-wire serial I/O (CSI0)/I • Note Channel 2: 3-wire serial I/O (CSI2)/I • Channel 3: 3-wire serial I/O (CSI3)/asynchronous serial interface (UART1) •...
Page 327: Configuration
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.1 Configuration CSIn includes the following hardware. Table 11-1. Configuration of CSIn Item Configuration Registers Serial I/O shift register n (SIOn) Control registers Serial operation mode register n (CSIMn) Serial clock select register n (CSISn) Remark n = 0, 2, 3 Figure 11-1.
Page 328: Csin Control Registers
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.2 CSIn control registers CSIn is controlled by the following registers. • Serial operation mode register n (CSIMn) • Serial clock select register n (CSISn) (1) Serial clock select register n (CSISn) and serial operation mode register n (CSIMn) CSISn is used to set the serial clock of serial interface channel n.
Page 329 CHAPTER 11 SERIAL INTERFACE FUNCTION After reset: 00H Address: CSIS0 FFFFF2A4H CSIS2 FFFFF2C4H CSIS3 FFFFF2D4H CSISn SCLn2 (n = 0, 2, 3) After reset: Address: CSIM0 FFFFF2A2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H <7> CSIMn CSIEn MODEn SCLn1 SCLn0 (n = 0, 2, 3) CSIEn SIOn operation enable/disable specification Shift register operation...
Page 330: Operations
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.3 Operations CSIn has the following two operation modes. • Operation stopped mode • 3-wire serial I/O mode (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. operation stopped mode, the SIn, SOn, and SCKn pins can be used as normal I/O port pins.
Page 331 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to devices such as peripheral I/O that include a clocked serial interface, and display controllers. This mode executes data transfers via three lines: a serial clock line (SCKn), a serial output line (SOn), and a serial input line (SIn).
Page 332 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmit data is held in the SOn latch and is output from the SOn pin.
Page 333: 3-Wire Serial I/O (Csi4): 8 To 16 Bits Variable
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3 3-Wire Serial I/O (CSI4): 8 to 16 Bits Variable CSI4 has the following two operation modes. (1) Operation stopped mode This mode is used when serial transfers are not performed. (2) 3-wire serial I/O mode (MSB/LSB-first switchable) This mode transfers variable data of 8 to 16 bits via three lines: a serial clock line (SCK4), a serial output line (SO4), and a serial input line (SI4).
Page 334 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-5. Block Diagram of 3-Wire Serial I/O (CSI4) Internal bus Direction controller Variable-length serial I/O shift register 4 (8 to 16 bits) Serial clock counter Interrupt INTCSI4 (8-/16-bit switchable) generator Baud rate Serial clock controller Selector generator SCK4...
Page 335 CHAPTER 11 SERIAL INTERFACE FUNCTION If the transfer bit length is set to other than 16 bits, when setting data to the shift register, be sure to align data from the lowest bit, regardless of whether the first transfer bit is MSB or LSB. Any data can be set to the unused higher bits, but in this case the data received after a serial transfer operation becomes 0.
Page 336: Csi4 Control Registers
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.2 CSI4 control registers CSI4 is controlled by the following registers. • Variable-length serial control register 4 (CSIM4) • Variable-length serial setting register 4 (CSIB4) • Baud rate generator source clock select register 4 (BRGCN4) •...
Page 337 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Variable-length serial setting register 4 (CSIB4) This register is used to set the operation format of serial interface channel 4. The bit length of a variable register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4.
Page 338 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Baud rate generator source clock select register 4 (BRGCN4) BRGCN4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCN4 to 00H. After reset: 00H Address: FFFFF2E6H BRGCN4 BRGN2 BRGN1 BRGN0 BRGN2 BRGN1 BRGN0 Source clock (f...
Page 339 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Baud rate generator output clock select register 4 (BRGCK4) BRGCK4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCK4 to 7FH. After reset: 7FH Address: FFFFF2E8H BRGCK4 BRGK6 BRGK5 BRGK4 BRGK3 BRGK2 BRGK1 BRGK0...
Page 340: Operations
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.3 Operations CSI4 has the following two operation modes. • Operation stopped mode • 3-wire serial I/O mode (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. In operation stopped mode, the SI4, SO4, and SCK4 pins can be used as normal I/O port pins.
Page 341 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to devices such as peripheral I/O that include a clocked serial interface, and display controllers. This mode executes data transfers via three lines: a serial clock line (SCK4), a serial output line (SO4), and a serial input line (SI4).
Page 342 CHAPTER 11 SERIAL INTERFACE FUNCTION The bit length of a variable-length register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of CSIB4. Data is transferred MSB first when bit 4 (DIR) is 1, and is transferred LSB first when DIR is 0. Figure 11-9.
Page 343 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8 to 16-bit units, specified by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4 (CSIB4). Each bit of data is transmitted or received in synchronization with the serial clock.
Page 344 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Transfer start A serial transfer becomes possible when the following two conditions have been satisfied. • The SIO4 operation control bit (CSIE4) = 1 • After a serial transfer, the internal serial clock is stopped. Serial transfer starts when the following operation is performed after the above two conditions have been satisfied.
Page 345: 3-Wire Serial I/O (Csi5, Csi6): 8 Or 16 Bits
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4 3-Wire Serial I/O (CSI5, CSI6): 8 or 16 Bits 11.4.1 Features • High-speed transfer: Maximum 4 Mbps • Half-duplex communications • Master mode or slave mode can be selected • Transmit data length: 8 bits or 16 bits can be set •...
Page 346: Configuration
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.2 Configuration CSIn includes the following hardware (n = 5, 6). Table 11-3. CSIn Configuration Item Configuration Registers Serial I/O shift register n, Ln (SIOn, SIOLn) Control registers Clocked serial interface mode register n (CSIMn) Clocked serial interface clock select register n (CSICKn) Clocked serial interface receive buffer register n, Ln (SIRBn, SIRBLn) Clocked serial interface read-only receive buffer register n, Ln (SIRBEn, SIRBELn)
Page 347 CHAPTER 11 SERIAL INTERFACE FUNCTION Transmission/reception of data is performed by the SIOn register (n = 0, 1). (1) Serial I/O shift register n (SIOn) The SIOn register is a 16-bit shift register that converts parallel data into serial data, and is used for both transmission and reception.
Page 348: Control Registers
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.3 Control registers CSIn is controlled by the following registers (n = 5, 6). • Clocked serial interface mode register n (CSIMn) • Clocked serial interface clock select register n (CSICKn) • Clocked serial interface receive buffer register n, Ln (SIRBn, SIRBLn) •...
Page 349 CHAPTER 11 SERIAL INTERFACE FUNCTION After reset: 00H Address: FFFFF240H, FFFFF260H Note CSIMn CSIEn TRMDn CCLn DIRn CSITn AUTOn CSOTn (n = 5, 6) CSIEn CSIn operation enable/disable specification CSIn operation enabled CSIn operation disabled The internal CSIn circuit can be reset asynchronously by setting the CSIEn bit to 0. For the SCKn and SOn pin output status when the CSIEn bit = 0, refer to 11.6.5 Output pins.
Page 350 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock select registers 5, 6 (CSICK5, CSICK6) The CSICKn register is an 8-bit register that controls the CSIn transfer operation (n = 5, 6). CSICKn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 351 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Clocked serial interface receive buffer registers 5, 6 (SIRB5, SIRB6) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (TRMDn bit of CSIMn register = 0), reception is started by reading data from the SIRBn register (n = 5, 6).
Page 352 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Clocked serial interface read-only receive buffer registers 5, 6 (SIRBE5, SIRBE6) The SIRBEn register is a 16-bit buffer register that stores receive data. SIRBEn is set by a 16-bit memory manipulation instruction (n = 5, 6). RESET input sets these registers to 0000H.
Page 353 CHAPTER 11 SERIAL INTERFACE FUNCTION (7) Clocked serial interface transmit buffer registers 5, 6 (SOTB5, SOTB6) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmit/receive mode is set (TRMDn bit of CSIMn register = 1), transmission is started by writing data to the SOTBn register (n = 5, 6).
Page 354 CHAPTER 11 SERIAL INTERFACE FUNCTION (9) Clocked serial interface initial transmit buffer registers 5, 6 (SOTBF5, SOTBF6) The SOTBFn register is a 16-bit buffer register that stores the initial transmit data in the repeat transfer mode. Transmission is not started even if data is written to the SOTBFn register (n = 5, 6). SOTBFn can be set by a 16-bit memory manipulation instruction.
Page 355 CHAPTER 11 SERIAL INTERFACE FUNCTION (11) Serial I/O shift registers 5, 6 (SIO5, SIO6) The SIOn register is a 16-bit shift register that converts parallel data into serial data. Data is shifted in (received) or shifted out (transmitted) starting from MSB or LSB. Transfer is not started even if the SIOn register is read (n = 5, 6).
Page 356: Operation
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.4 Operation CSIn is has the following two operation modes (n = 5, 6). • Single transfer mode • Repeat transfer mode (1) Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by reading the receive data buffer register (SIRBn/SIRBLn) (n = 5, 6).
Page 357 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-13. Timing Chart in Single Transfer Mode (1/2) (a) In transmit/receive mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 0 SCKn (I/O) (55H)
Page 358 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-13. Timing Chart in Single Transfer Mode (2/2) (b) In transmit/receive mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 1 SCKn (I/O) (55H)
Page 359 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKPn bit of CSICn register) and data phase selection (DAPn bit of CSICn register) under the following conditions. •...
Page 360 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-14. Timing Chart According to Clock Phase Selection (2/2) (c) When CKPn bit = 0, DAPn bit = 1 SCKn (I/O) SIn (input) DO6 DO5 DO4 DO3 DO2 DO1 SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit (d) When CKPn bit = 1, DAPn bit = 1 SCKn (I/O)
Page 361 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Transmission/reception completion interrupt request signals (INTCSI5, INTCSI6) INTCSIn is set (1) upon completion of data transmission/reception. Caution The delay mode (CSITn bit = 1) is valid only in the master mode (bits CKSn2 to CKSn0 of the CSICKn register are not 111B).
Page 362 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-15. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKPn bit = 1, DAPn bit = 1 Input clock SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1.
Page 363 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTOn bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 364 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-16. Repeat Transfer (Receive-Only) Timing Chart SCKn (I/O) SIn (input) din-1 din-2 din-3 din-4 din-5 SIOLn din-5 register SIRBLn din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg_RD SIRBn (dummy) SIRBn (d1) SIRBn (d2) SIRBn (d3) SIOn (d5) CSOTn bit INTCSIn...
Page 365 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTOn bit of CSIMn register = 1) and the transmission/reception mode (TRMDn bit of CSIMn register = 1) <2> Write the first data to the SOTBFn register. <3>...
Page 366 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-17. Repeat Transfer (Transmission/Reception) Timing Chart SCKn (I/O) SOn (output) dout-1 dout-2 dout-3 dout-4 dout-5 SIn (input) din-1 din-2 din-3 din-4 din-5 SOTBFLn dout-1 register SOTBLn dout-2 dout-3 dout-4 dout-5 register SIOLn din-5 register SIRBLn din-1 din-2...
Page 367 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared within the period shown below. Figure 11-18. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length is 8 bits, operation mode: CKPn bit = 0, DAPn bit = 0 SCKn (I/O) INTCSIn...
Page 368 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-18. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length is 8 bits, operation mode: CKPn bit = 0, DAPn bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 6.5 SCKn cycles (d) When data length is 16 bits, operation mode: CKPn bit = 0, DAPn bit = 1 SCKn (I/O)
Page 369 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If the SIRBn register or the SOTBn register is accessed when the transfer reservation period is over, the following occurs.
Page 370 CHAPTER 11 SERIAL INTERFACE FUNCTION (ii) In case of contention between interrupt request and register access Since continuous transfer has stopped once, the transfer is executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 11-20). In the transmit/receive mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 371: Output Pins
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.5 Output pins (1) SCKn pin When CSIn operation is disabled (CSIEn bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 5, 6). Table 11-4. SCKn Pin Output Status CKPn CKSn2 CKSn1...
Page 372: I 2 C Bus
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5 I C Bus To use the I C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open-drain output. C0 and I C1 have the following two modes. • Operation stopped mode •...
Page 373 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-21. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Slave address Start condition Clear register n (SVAn)
Page 374 CHAPTER 11 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 11-22. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 375: Configuration
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.1 Configuration Cn includes the following hardware (n = 0, 1). Table 11-6. Configuration of I Item Configuration Registers IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) Control registers IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1)
Page 376 CHAPTER 11 SERIAL INTERFACE FUNCTION (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Eighth or ninth clock of the serial clock (set by WTIMn bit) •...
Page 377: I 2 C Control Registers
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.2 I C control registers C0 and I C1 are controlled by the following registers. • IIC control registers 0, 1 (IICC0, IICC1) • IIC status registers 0, 1 (IICS0, IICS1) • IIC flag registers 0, 1 (IICF0, IICF1) •...
Page 378 CHAPTER 11 SERIAL INTERFACE FUNCTION (1/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Cn operation enable/disable specification Operation stopped. IIC status register n (IICSn) preset. Internal operation stopped. Operation enabled.
Page 379 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/4) WRELn Wait cancellation control Wait not cancelled Wait cancelled. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1) • Automatically cleared after execution •...
Page 380 CHAPTER 11 SERIAL INTERFACE FUNCTION (3/4) ACKEn Acknowledge control Acknowledgement disabled. Acknowledgement enabled. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1. Note Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)
Page 381 CHAPTER 11 SERIAL INTERFACE FUNCTION (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
Page 382 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) IIC status registers 0, 1 (IICS0, IICS1) These registers indicate the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H.
Page 383 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) • When a start condition is detected •...
Page 384 CHAPTER 11 SERIAL INTERFACE FUNCTION (3/3) ACKDn Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKD = 1) • When a stop condition is detected • After the SDAn line is set to low level at the rising edge •...
Page 385 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) IIC flag registers 0, 1 (IICF0, IICF1) These registers set the I Cn operation mode and indicate the I C bus status (n = 0, 1). IICFn can be set by an 8-bit or 1-bit memory manipulation instruction. IICRSVn enables/disables the communication reservation function (see 11.5.12 Communication reservation).
Page 386 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/2) STCENn Initial start enable trigger Start conditions cannot be generated until a stop condition is detected following operation enable (IICEn = Start conditions can be generated even if a stop condition is not detected following operation enable (IICEn = 1).
Page 387 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) IIC clock expansion registers 0, 1 (IICCE0, IICCE1), IIC function expansion registers 0, 1 (IICX0, IICX1), IIC clock select registers 0, 1 (IICCL0, IICCL1) These registers are used to set the transfer clock for the I Cn bus.
Page 388 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/2) SMCn Operation mode switching Operates in standard mode. Operates in high-speed mode. DFCn Digital filter operation control Digital filter off. Digital filter on. Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFCn switching (on/off). Selection clock Settable main clock frequency (f ) range...
Page 389 CHAPTER 11 SERIAL INTERFACE FUNCTION (a) I Cn transfer clock setting method The I Cn transfer clock frequency (f ) is calculated using the following expression (n = 0, 1). = 1/(m × T + t m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see the descriptions for bits IICCEn1, IICCEn0, CLXn, SMCn, CLn1, and CLn0 in 11.5.2 (4).) : SCLn rise time SCLn fall time...
Page 390: I 2 C Bus Mode Functions
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.3 C bus mode functions (1) Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0, 1). SCLn ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 391: I C Bus Definitions And Control Methods
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. The transfer timing for the “start condition”, “data”, and “stop condition” output via the I C bus’s serial data bus is shown below.
Page 392 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 393 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 394 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 395 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Stop condition When the SCLn pin is high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0, 1). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 396 CHAPTER 11 SERIAL INTERFACE FUNCTION (6) Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1).
Page 397 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-30. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait) IICn SCLn...
Page 398: C Interrupt Requests (Intiicn)
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 399 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7 L1: IICSn = 10XXX110B...
Page 400 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B...
Page 401 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (matches with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 402 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 403 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 404 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0001X110B...
Page 405 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
Page 406 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
Page 407 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
Page 408 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0010X010B...
Page 409 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn = 00000001B ∆: Generated only when SPIEn = 1 Remark n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss)
Page 410 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
Page 411 CHAPTER 11 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
Page 412 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) ∆...
Page 413 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
Page 414 CHAPTER 11 SERIAL INTERFACE FUNCTION (e) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICSn = 1000X110B ∆ 2: IICSn = 01000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: don’t care Dn = D6 to D0 n = 0, 1...
Page 415 CHAPTER 11 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1 STTn = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B ∆...
Page 416: Interrupt Request (Intiicn) Generation Timing And Wait Control
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) in IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 11-7.
Page 417: Address Match Detection Method
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.7 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIICn) occurs when a local address has been set to slave address register n (SVAn) and when the address set to SVAn matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1).
Page 418: Arbitration
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to Note ), communication among the master devices is performed while the number of clocks are being adjusted until the data differs.
Page 419: Wakeup Function
CHAPTER 11 SERIAL INTERFACE FUNCTION Table 11-9. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 420: Communication Reservation
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.12 Communication reservation (1) When communication reservation function is enabled (IICRSVn of IICFn = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 421 CHAPTER 11 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 11-32. Communication Reservation Timing STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn STDn SCLn SDAn Output by master with bus access IICn: IIC shift register n STTn:...
Page 422 CHAPTER 11 SERIAL INTERFACE FUNCTION The communication reservation flowchart is illustrated below. Figure 11-34. Communication Reservation Flowchart (1) SET1 STTn Sets STTn bit (communication reservation). Define communication Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). reservation Secures wait period set by software (see Table 11-10).
Page 423 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) When communication reservation function is disabled (IICRSVn of IICFn register = 1) When the STTn bit of the IICCn register is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
Page 424 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-36. Communication Reservation Flowchart (2) IICBSYn = 0 ? SET1 STTn Set STTn bit Wait time (Table 11-11) is Wait secured by software STCFn = 0 ? Bus communicating status Master communication ← ××H IICn IICn write operation stopped...
Page 425: Cautions
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.13 Cautions (1) When STCENn of IIC flag register n (IICFn) = 0 Immediately after the I Cn operation is enabled, the bus communication status (IICBSYn of IICFn register = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 426: Communication Operations
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.14 Communication operations (1) Master operations (1) The following shows the flowchart for master communication when the communication reservation function is enabled (IICRSVn = 0) and the master operation is started after a stop condition is detected (STCENn = 0). Figure 11-37.
Page 427 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Master operations (2) The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn = 1) and the master operation is started without detecting a stop condition (STCENn = 1). Figure 11-38.
Page 428 CHAPTER 11 SERIAL INTERFACE FUNCTION Slave operation The following shows the flowchart for slave communication. Figure 11-39. Slave Operation Flowchart START ← ××H IICCn IICEn = 1 INTIICn = 1? EXCn = 1? Communicate? COIn = 1? LRELn = 1 No (receive) TRCn = 1? WTIMn = 0...
Page 429: Timing Of Data Communication
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 430 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-40. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn...
Page 431 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-40. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn...
Page 432 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-40. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
Page 433 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-41. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn...
Page 434 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-41. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn...
Page 435 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-41. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn...
Page 436: Asynchronous Serial Interface (Uart0 To Uart3)
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.6 Asynchronous Serial Interface (UART0 to UART3) UARTn (n = 0 to 3) has the following two operation modes. (1) Operation stop mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) Asynchronous serial interface mode This mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received.
Page 437 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-42. Block Diagram of UARTn Internal bus Receive buffer register n (RXBn) Receive shift register RXDn n (RXn) Transmit shift register TXDn n (TXSn) Receive control INTSRn parity check Transmit control INTSTn parity addition Baud rate generator to f Selector...
Page 438: Uartn Control Registers
CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn).
Page 439 CHAPTER 11 SERIAL INTERFACE FUNCTION (1) Asynchronous serial interface mode registers 0 to 3 (ASIM0 to ASIM3) ASIMn is an 8-bit register that controls UARTn’s serial transfer operations. ASIMn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 440 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0 to 3 (ASIS0 to ASIS3) When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. ASISn can be read using an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 441 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0 to 3 (BRGC0 to BRGC3) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H Address: BRGC0: FFFFF304H...
Page 442 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) These registers set the UARTn source clock. BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction (n = 0 to 3). RESET input sets these registers to 00H. After reset: 00H Address: BRGMC01: FFFFF320H...
Page 443: Operations
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.6.3 Operations UARTn has the following two operation modes. • Operation stopped mode • Asynchronous serial interface mode (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. In operation stopped mode, pins can be used as ordinary port pins.
Page 444 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode This mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates.
Page 445 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-45. ASISn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: ASIS0: FFFFF302H ASIS1: FFFFF312H ASIS2: FFFFF232H ASIS3: FFFFF2B2H <2> <1> <0> ASISn OVEn (n = 0 to 3) Parity error flag No parity error Parity error (Transmit data parity does not match) Framing error flag...
Page 446 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-46. BRGCn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: BRGC0: FFFFF304H BRGC1: FFFFF314H BRGC2: FFFFF234H BRGC3: FFFFF2B4H BRGCn MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 (n = 0 to 3) Input clock selection ×...
Page 447 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-47. BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) After reset: 00H Address: BRGMC01: FFFFF320H BRGMC11: FFFFF322H BRGMC21: FFFFF23CH BRGMC31: FFFFF2BCH BRGMCn1 TPSn3 (n = 0 to 3) After reset: 00H Address: BRGMC00: FFFFF30EH BRGMC10: FFFFF31EH BRGMC20: FFFFF23AH BRGMC30: FFFFF2BAH...
Page 448 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Baud rate The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. • Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock.
Page 449 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-48. Allowable Baud Rate Error Range (When k = 16), Including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal...
Page 450 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Communication operations (a) Data format As shown in Figure 11-49, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0 to 3).
Page 451 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected.
Page 452 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Transmission A transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting a transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmission completion interrupt (INTSTn) is issued.
Page 453 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Reception A receive operation is enabled when bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn) is set to 1, and input via the RXDn pin is sampled. The serial clock specified by BRGCn is used when sampling the RXDn pin. When the RXDn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 454 CHAPTER 11 SERIAL INTERFACE FUNCTION (e) Receive error There are three types of error during a receive operation: parity errors, framing errors, and overrun errors. When, as the result of data reception, an error flag is set in asynchronous serial interface status register n (ASISn).
Page 455: Standby Function
CHAPTER 11 SERIAL INTERFACE FUNCTION 11.6.4 Standby function (1) Operation in HALT mode Serial transfer is performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are held.
Page 456: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 Function The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The V850/SC1, V850/SC2, and V850/SC3 support low-speed conversion and a low-power-consumption mode. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified).
Page 457 CHAPTER 12 A/D CONVERTER The block diagram is shown below. Figure 12-1. Block Diagram of A/D Converter ADCV ANI0 ANI1 ANI2 Sample & hold circuit ANI3 ANI4 Voltage comparator ANI5 ANI6 ANI7 ANI8 ADCGND ANI9 ANI10 Successive ANI11 ADCGND approximation register (SAR) Edge ADTRG...
Page 458: Configuration
CHAPTER 12 A/D CONVERTER 12.2 Configuration The A/D converter includes the following hardware. Table 12-1. Configuration of A/D Converter Item Configuration Analog inputs 12 channels (ANI0 to ANI11) Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Control registers A/D converter mode register 1 (ADM1)
Page 459 CHAPTER 12 A/D CONVERTER (6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input analog signals to be converted into digital signals. Pins other than ones selected as analog input with the analog input channel specification register (ADS) can be used as input ports.
Page 460: Control Registers
CHAPTER 12 A/D CONVERTER 12.3 Control Registers The A/D converter is controlled by the following registers. • A/D converter mode register 1 (ADM1) • Analog input channel specification register (ADS) • A/D converter mode register 2 (ADM2) (1) A/D converter mode register 1 (ADM1) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger.
Page 461 CHAPTER 12 A/D CONVERTER (2/2) ADPS Selection of conversion time Note 1 Conversion time Note 2 + stabilization time 20 MHz 18.87 MHz 16 MHz 8.4 µ s 8.9 µ s 168/f Setting prohibited 6.0 µ s 6.4 µ s 7.5 µ...
Page 462 CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the port for inputting the analog voltage to be converted into a digital signal. ADS is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets ADS to 00H. After reset: Address: FFFFF3C2H ADS3...
Page 463: Operation
CHAPTER 12 A/D CONVERTER 12.4 Operation 12.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>...
Page 464 CHAPTER 12 A/D CONVERTER Figure 12-2. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCR result INTAD A/D conversion is successively executed until bit 7 (ADCS) of A/D converter mode register 1 (ADM1) is reset (0) by software.
Page 465: Input Voltage And Conversion Result
CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows: ×...
Page 466: A/D Converter Operation Mode
CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. A/D conversion can be started in the following two ways: •...
Page 467 CHAPTER 12 A/D CONVERTER (1) A/D conversion by hardware start A/D conversion is on standby if bit 6 (TRG) and bit 7 (ADCS) of A/D converter mode register 1 (ADM1) are set to 1. When an external trigger signal is input, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 468 CHAPTER 12 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) and bit 7 (ADCS) of A/D converter mode register 1 (ADM1) are set to 1, the A/D converter starts converting the voltage applied to an analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 469: Low-Power-Consumption Mode
CHAPTER 12 A/D CONVERTER 12.5 Low-Power-Consumption Mode The V850/SC1, V850/SC2, and V850/SC3 feature a function that can cut or connect the current between ADCV and the series resistor string. Switching can be performed by setting A/D converter mode register 2 (ADM2). When not using the A/D converter, cut off the tap selector (a function to reduce current) from the voltage supply block (ADCV ) while A/D conversion is stopped (ADCS = 0) to cut the current consumption.
Page 470 CHAPTER 12 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, it is necessary to prevent noise from being superimposed on the ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown below is recommended.
Page 471 CHAPTER 12 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten.
Page 472 CHAPTER 12 A/D CONVERTER (7) ADCV The ADCV pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the V pin to the ADCV pin as shown below.
Page 473: Chapter 13 Dma Functions
CHAPTER 13 DMA FUNCTIONS 13.1 Functions The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as the serial interfaces, timer, or A/D converter). This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units. maximum number of transfers is 256 (when transferring data in 8-bit units).
Page 474: Configuration
CHAPTER 13 DMA FUNCTIONS 13.3 Configuration Figure 13-1. DMA Block Diagram DMA transfer DMA transfer start factor request control (INT signal) DMA peripheral I/O address DMA start factor expansion register n (DIOAn) register (DMAS) DMA byte count register n DMA channel control (DBCn) register n (DCHCn) Channel...
Page 475: Control Registers
CHAPTER 13 DMA FUNCTIONS 13.4 Control Registers (1) DMA peripheral I/O address registers 0 to 5 (DIOA0 to DIOA5) These registers are used to set the peripheral I/O register address for DMA channel n. These registers can be read/written in 16-bit units. After reset: Undefined Address:...
Page 476 CHAPTER 13 DMA FUNCTIONS The following shows the correspondence between the DRAn setting value and the internal RAM area. (a) V850/SC1 ( µ µ µ µ PD703068Y, 70F3089Y) V850/SC2 ( µ µ µ µ PD703069Y, 70F3089Y) V850/SC3 ( µ µ µ µ PD703088Y, 703089Y, 70F3089Y) Set the DRAn register to a value in the range of 0000H to 0FFFH or 1000H to 3FFFH (n = 0 to 5).
Page 477 CHAPTER 13 DMA FUNCTIONS (3) DMA byte count registers 0 to 5 (DBC0 to DBC5) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during DMA transfer. The transfer count is decremented by 1 per transfer if the transfer is a byte (8-bit) transfer, and by 2 per transfer if the transfer is a 16-bit transfer.
Page 478 CHAPTER 13 DMA FUNCTIONS (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) These registers are used to control the DMA transfer operation mode for DMA channel n. Refer to (6) Start factor settings for the setting of the TTYPn1 and TTYPn0 bits. These registers can be read/written in 8- or 1-bit units.
Page 479 CHAPTER 13 DMA FUNCTIONS (6) Start factor settings The DMA start factor is set using bits 2 to 0 (DMAS2 to DMAS0) of the DMA start factor expansion register (DMAS) in combination with bits 4 and 3 (TTYPn1, TTYPn0) of DMA channel control registers 0 to 5 (DCHC0 to DCHC5)(n = 0 to 5).
Page 480 CHAPTER 13 DMA FUNCTIONS Table 13-2. Start Factor Settings Channel n DMAS2 DMAS1 DMAS0 TTYPn1 TTYPn0 DMA Transfer Start Factor Setting INTCSI0/INTIIC0 INTCSI5 INTAD INTTM00 INTCSI0/INTIIC0 INTCSI1/INTSR0 INTST0 INTP0 INTSR3 INTCSI2/INTIIC1 INTCSI3/INTSR1 INTP6 INTIE1 (setting prohibited for other than V850/SC2) INTAD INTCSI6 INTCSI3/INTSR1...
Page 481: Operation
CHAPTER 13 DMA FUNCTIONS 13.5 Operation When a DMA transfer request is generated during CPU processing, DMA transfer is started after the current CPU processing has finished. Regardless of the transfer direction, 4 CPU clocks (f ) are required for one DMA transfer. The 4 CPU clocks are divided as follows.
Page 482: Cautions
CHAPTER 13 DMA FUNCTIONS Figure 13-4. Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously DAM0 DAM1 DAM2 DAM3 DAM4 DAM5 processing processing processing processing processing processing processing processing processing processing processing processing processing Transfer requests DMA0 to DMA5 are generated simultaneously DMA operation stops only in the IDLE/STOP mode.
Page 483 CHAPTER 13 DMA FUNCTIONS Figure 13-5. When Interrupt Servicing Occurs Twice During DMA Operation (1/2) (a) Normal interrupt servicing Interrupt servicing routine Main routine Interrupt request flag (xxIFn) is cleared (0). Interrupt request RETI (b) Interrupt servicing when interrupt servicing occurs twice Interrupt servicing routine Main routine Interrupt request flag (xxIFn) is...
Page 484 CHAPTER 13 DMA FUNCTIONS Figure 13-5. When Interrupt Servicing Occurs Twice During DMA Operation (2/2) (c) Countermeasure (use condition (i)) Main routine Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0). Bit manipulation instruction to xxIFn Interrupt request The interrupt is serviced in the EI state (interrupt enable state) (the interrupt is not serviced immediately after bit manipulation instruction execution).
Page 485: Chapter 14 Reset Function
CHAPTER 14 RESET FUNCTION 14.1 General There are three methods used to generate a reset signal. (1) External reset by RESET signal input (2) Internal reset by watchdog timer loop time detection (watchdog timer overflow) (3) Internal reset by power-on-clear (POC) (1) External reset by RESET signal input When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings.
Page 486: Pin Operations
CHAPTER 14 RESET FUNCTION 14.2 Pin Operations During the system reset period, almost all pins are set to high impedance (except for RESET, X2, XT2, CPUREG, , ADCV , ADCGND, PORTV to PORTV , PORTGND0, PORTGND1, GND0, GND1, GND2, and /IC).
Page 487 CHAPTER 14 RESET FUNCTION Figure 14-3. System Reset Timing by Power-on-Clear (a) At power application Oscillation Reset period Normal operation stabilization (oscillation stopped) (reset processing) time wait 3.5 V Power-on-clear voltage (3.5 V) Internal reset signal Hi-Z I/O port pin (b) In STOP mode Hi-Z STOP instruction execution...
Page 488: Power-On-Clear Operation
CHAPTER 14 RESET FUNCTION 14.3 Power-on-Clear Operation The V850/SC1, V850/SC2, and V850/SC3 include a power-on-clear circuit (POC), through which low-voltage pin voltage detection (4.2 ±0.3 V) can be performed by means of the POC status register (POCS). detection and V (1) POC status register (POCS) When a power-on-clear is generated, bit 0 of the POCS register is set to 1.
Page 489 CHAPTER 14 RESET FUNCTION (2) VM45 control register (VM45C) The detection status (detected/undetected) according to the VM45 bit of the POCS register can be output (monitored) at the VM45/P176 pin via control by the VM45C register. After reset: 00H Address: FFFFF07CH POCS VM45C1 VM45C0...
Page 490: Chapter 15 Regulator
CHAPTER 15 REGULATOR 15.1 Outline The V850/SC1, V850/SC2, and V850/SC3 incorporate a regulator to realize a 5 V single power supply, low power consumption, and to reduce noise. This regulator supplies a voltage obtained by stepping down the V power supply voltage to oscillation block and on-chip logic circuits (excluding the A/D converter and output buffers).
Page 491: Chapter 16 Rom Correction Function
CHAPTER 16 ROM CORRECTION FUNCTION 16.1 General The ROM correction function provided in the V850/SC1, V850/SC2, and V850/SC3 is a function that replaces part of a program in the mask ROM with a program in the internal RAM. First, the instruction of the address where the program replacement should start (correction address) is replaced with the JMP r0 instruction and instructed to jump to 00000000H.
Page 492: Rom Correction Peripheral I/O Registers
CHAPTER 16 ROM CORRECTION FUNCTION 16.2 ROM Correction Peripheral I/O Registers 16.2.1 Correction control register (CORCN) CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction when the correction address set to the correction address register (CORADn) matches the fetch address (n = 0 to 3). Whether match detection by a comparator is enabled or disabled can be set for each channel.
Page 493: Correction Address Registers 0 To 3 (Corad0 To Corad3)
CHAPTER 16 ROM CORRECTION FUNCTION 16.2.3 Correction address registers 0 to 3 (CORAD0 to CORAD3) CORADn sets the start address of the instruction to be corrected (correction address) in the ROM. Up to four points of the program can be corrected at once since the V850/SC1, V850/SC2, and V850/SC3 have four correction address registers (CORADn) (n = 0 to 3).
Page 494 CHAPTER 16 ROM CORRECTION FUNCTION Figure 16-2. ROM Correction Operation and Program Flow START(reset vector) CORRQn = 0? Microcontroller initialization Clears CORRQn flag. JMP channel n correct code address The address of the internal RAM that Data for ROM correction setting is loaded stores the correction code of channel n from an external memory into the internal should be preset before the instruction...
Page 495: Chapter 17 Flash Memory ( Μ Μ Μ Μ Pd70F3089Y)
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 The µ PD70F3089Y is the flash memory version of the V850/SC1, V850/SC2, and V850/SC3 and incorporates a 512 KB flash memory. Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions.
Page 496: Write/Read Time
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.1.2 Write/read time The write/read time is shown below. Write time: 50 µ s/byte Read time: 50 ns (cycle time) 17.2 Writing with Flash Programmer Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory is rewritten after the V850/SC1, V850/SC2, and V850/SC3 are mounted on the target system.
Page 497 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 Figure 17-1. Example of Wiring of Adapter for Flash Programming (FA-144GJ-UEN) Note 75 74 73 µ PD70F3089Y Connect to GND. Connect to VDD. µ /RESET RESERVE/HS Note The µ PD70F3089Y cannot be supplied with the clock from the CLK pin of the flash programmer (PG- FP3).
Page 498 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 Remarks 1. Handle the pins not described above in accordance with the recommended connection of unused pins (refer to 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins).
Page 499: Programming Environment
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850/SC1, V850/SC2, and V850/SC3. Figure 17-2. Environment Required for Writing Programs to Flash Memory RS-232C PORTV to PORTV...
Page 500 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 (2) CSI0 Serial clock: Up to 1 MHz (MSB first) Figure 17-4. Communication with Dedicated Flash Programmer (CSI0) PORTV to PORTV GND0 to GND2, PORTGND0, PORTGND1 RESET RESET Dedicated flash V850/SC1, V850/SC2, programmer V850/SC3...
Page 501 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 Table 17-2. Signal Generation of Dedicated Flash Programmer (PG-FP3) PG-FP3 V850/SCx Connection CSI0 + HS Signal Name Pin Function Pin Name CSI0 UART0 Output Writing voltage voltage generation/ voltage monitoring PORTV PORTV −...
Page 502: Pin Connection
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operating mode to the flash memory programming mode.
Page 503: Serial Interface Pin
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.5.2 Serial interface pin The following shows the pins used by each serial interface. Table 17-3. Pins Used by Serial Interfaces Serial Interface Pins Used CSI0 SO0, SI0, SCK0 CSI0 + HS SO0, SI0, SCK0, P15 UART0 TXD0, RXD0...
Page 504 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 (2) Malfunction of other device When connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or set so that the input signal to the other device is ignored.
Page 505: Reset Pin
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin that is connected to the reset signal generator on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 506: Programming Method
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.6 Programming Method 17.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 17-10. Procedure for Manipulating Flash Memory Start Supplies RESET pulse Switch to flash memory programming mode Select communication mode Manipulate flash memory End?
Page 507: Selection Of Communication Mode
FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 17.6.3 Selection of communication mode In the V850/SC1, V850/SC2, and V850/SC3, the communication mode is selected by inputting pulses (16 pulses max.) to V pin after switching to the flash memory programming mode. The V pulse is generated by the dedicated flash programmer.
Page 508 FLASH MEMORY ( µ µ µ µ PD70F3089Y) CHAPTER 17 The following shows the commands for flash memory control of the V850/SC1, V850/SC2, and V850/SC3. All of these commands are issued from the dedicated flash programmer, and the V850/SC1, V850/SC2, and V850/SC3 perform the various processings corresponding to the commands.
Page 509: Chapter 18 Iebus Controller (V850/Sc2)
CHAPTER 18 IEBus CONTROLLER (V850/SC2) The IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To implement the IEBus with the V850/SC2, an external IEBus driver and receiver are necessary because they are not provided.
Page 510: Determination Of Bus Mastership (Arbitration)
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration grants one of the units the permission to occupy the bus.
Page 511: Broadcast Communication
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.1.5 Broadcast communication Normally, transmission or reception is performed between the master unit and its mating slave unit on a one-to-one basis. During broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units.
Page 512 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (2) Broadcast bit This bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcast communication) as the other party of communication. When the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated.
Page 513 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 18-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake.
Page 514 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (5) Control field The master outputs the operation it requires the slave to perform, by using this field. The configuration of the control field is as shown in Figure 18-4. If the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field.
Page 515 CHAPTER 18 IEBus CONTROLLER (V850/SC2) If the control bit received from the master unit is not as shown in Table 18-3, the unit locked by the master unit reject accepting the control bit, and does not output the acknowledge bit. Table 18-3.
Page 516 CHAPTER 18 IEBus CONTROLLER (V850/SC2) Table 18-5. Control Field Acknowledge Signal Output Conditions (a) When received control data is AH, BH, EH, FH Communication Communication Lock status Master unit Slave Slave reception Received control data type target (SLVRQ) (LOCK) judgment transmission enable (ENSLVRX)
Page 517 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 18-5. Table 18-6 shows the relationship between the telegraph length bit and the number of transmit data.
Page 518 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 18-6.
Page 519 CHAPTER 18 IEBus CONTROLLER (V850/SC2) Caution Do not operate a master reception in broadcast communication, because the slave unit cannot be defined and a data transfer cannot be performed correctly. (8) Parity bit The parity bit is used to check to see if the transmit data has no error. The parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits.
Page 520: Transfer Data
CHAPTER 18 IEBus CONTROLLER (V850/SC2) Cautions 1. Even when the slave transmission enable flag (ENSLVTX) is not set (1), ACK is always returned if slave status request control data is received. Even when slave reception enable flag (ENSLVRX) is not set (1), NACK is always returned by the acknowledge bit in the control field if data/command writing control data is acknowledged.
Page 521 CHAPTER 18 IEBus CONTROLLER (V850/SC2) Figure 18-7. Bit Configuration of Slave Status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 1 Bit 0 Meaning Transmit data is not written in IEBus data register (DR) Transmit data is written in IEBus data register (DR) Note 2 Bit 1...
Page 522 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 18-8.
Page 523: Bit Format
CHAPTER 18 IEBus CONTROLLER (V850/SC2) (c) Lock setting conditions Control Data Broadcast Communication Individual Communication Communication End Frame End Communication End Frame End Note 3H, 6H Cannot be locked Lock set AH, BH Cannot be locked Cannot be locked Cannot be locked Lock set 0H, 4H, 5H, EH, FH Cannot be locked...
Page 524: Iebus Controller Configuration
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.2 IEBus Controller Configuration The block diagram of the IEBus controller is shown below. Figure 18-10. IEBus Controller Block Diagram CPU interface block     BCR(8) UAR(12) SAR(12) PAR(12) CDR(8) DLR(8) DR(8) USR(8) ISR(8) SSR(8) SCR(8)
Page 525 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (a) CPU interface block This is a control block that interfaces between the CPU (V850/SC2) and the IEBus. (b) Interrupt control block This control block transfers interrupt request signals from the IEBus to the CPU. (c) Internal registers These registers set data to the control registers and fields that control the IEBus (for the internal registers, refer to 18.3 Internal Registers of IEBus Controller).
Page 526: Internal Registers Of Iebus Controller
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.3 Internal Registers of IEBus Controller 18.3.1 Internal register list Table 18-7. Internal Registers of IEBus Controller Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √...
Page 527: Internal Registers
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.3.2 Internal registers The internal registers incorporated in the IEBus controller are described below. (1) IEBus control register (BCR) After reset: 00H Address: FFFFF3E0H <7> <6> <5> <4> <3> ENIEBUS MSTRQ ALLRQ ENSLVTX ENSLVRX ENIEBUS Communication enable flag IEBus unit stopped IEBus unit active...
Page 528 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (a) Communication enable flag (ENIEBUS)...Bit 7 <Set/reset conditions> Set: By software Reset: By software Caution Make both of the following settings before setting the ENIEBUS flag. • • • • Set the interrupt enable (EI) status and enable interrupt servicing of INTIE2 (IEBMK = •...
Page 529 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (d) Slave transmission enable flag (ENSLVTX)...Bit 4 <Set/reset conditions> Set: By software Reset: By software Cautions 1. Clear the ENSLVTX flag before setting the MSTRQ flag when making a master request. If a slave transmission request is sent in slave mode while the ENSLVTX flag is unset, NACK in the control field will be returned.
Page 530 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (2) IEBus unit address register (UAR) This register sets the unit address of the IEBus unit. This register must always be set before starting communication. Sets the unit address (12 bits) to bits 11 to 0. 11 10 Address After reset...
Page 531 CHAPTER 18 IEBus CONTROLLER (V850/SC2) After reset: 01H Address: FFFFF3E8H SELCL2 SELCL1 SELCL0 SELCL2 SELCL1 SELCL0 Function Reads slave status Undefined Undefined Reads data and locks Reads lock address (lower 8 bits) Reads lock address (lower 4 bits) Reads slave status and unlocks Reads data Undefined Undefined...
Page 532 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (c) Slave status return operation When the IEBus receives a request to transfer from master to slave status (control data: 0H, 6H) or a lock address request (4H, 5H), whether ACK in the control field is returned or not depends on the status of the IEBus unit.
Page 533 CHAPTER 18 IEBus CONTROLLER (V850/SC2) Figure 18-12. Interrupt Generation Timing (for (2) and (5)) Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) Terminated by communication error INTIE2 Flag reset by CPU processing Flag set by reception of 0H, 4H, 5H, 6H STATUSF flag...
Page 534 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (6) IEBus telegraph length register (DLR) (a) When transmission unit ... Master transmission, slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. This register must be set in advance before transmission.
Page 535 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (7) IEBus data register (DR) The IEBus data register (DR) sets the communication data (8 bits) to bits 7 to 0. Remark The IEBus telegraph length register is divided into a writing side and a reading side, making it impossible for the written data to be readout as is.
Page 536 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (8) IEBus unit status register (USR) After reset: 00H Address: FFFFF3EEH <6> <5> <4> <3> <2> SLVRQ ARBIT ALLTRNS LOCK Slave request flag SLVRQ No request from master to slave Request from master to slave Arbitration result flag ARBIT Arbitration win...
Page 537 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (b) Contention result flag (ARBIT)...Bit 5 This flag shows the contention result. <Set/reset conditions> Set: This flag is set if, following a master request, the data output by the IEBus unit during the arbitration period and the bus line data do not match. Reset: This flag is reset at the start bit timing.
Page 538 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (e) Lock status flag (LOCK)...Bit 2 A flag that indicates whether the unit is locked. <Set/reset conditions> Set: When the communication end flag goes low level and the frame end flag goes high level after receipt of a lock specification (3H, 6H, AH, BH) in the control field.
Page 539 CHAPTER 18 IEBus CONTROLLER (V850/SC2) After reset: 00H R/W Address: FFFFF3F0H <6> <5> <4> <3> <2> STARTF STATUSF ENDTRNS ENDFRAM IEERR IEERR Communication error flag (during communication) No communication error Communication error STARTF Start interrupt flag Start interrupt not generated Start interrupt generated STATUSF Status transmission flag (slave)
Page 540 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (a) Communication error flag (IEERR)...Bit 6 A flag that indicates the detection of an error during communication. <Set/reset conditions> Set: When a timing error, parity error (except in the data field), NACK reception (except for data field), underrun error, or overrun error (which occurs in broadcast communication) occurs.
Page 541 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (f) Communication error triggers • • • • Timing error Occurrence conditions: Occurs if the high/low level width of the communication bit has shifted from the prescribed value. Remark: The respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer.
Page 542 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (g) Overrun error - supplementary details (i) When the frame ends in the overrun state during individual communication reception If the DR register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (INTIE2) is generated.
Page 543 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (10) IEBus slave status register (SSR) This register indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, the CPU reads this register, and writes a slave status to the IEBus data register (DR) to transmit the slave status.
Page 544 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (11) IEBus success count register (SCR) The IEBus success count register (SCR) indicates the number of remaining communication bytes. This register reads the count value of the counter that decrements the value set by the telegraph length register by ACK in the data field.
Page 545 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (12) IEBus communication count register (CCR) The IEBus communication count register (CCR) indicates the number of remaining bytes in the communication byte number specified in the communication mode. Bits 7 to 0 of the IEBus communication count register (CCR) indicate the number of transfer bytes. This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1 and is decremented during the ACK period of the data field regardless of ACK/NACK.
Page 546: Interrupt Operations Of Iebus Controller
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.4 Interrupt Operations of IEBus Controller 18.4.1 Interrupt control block Interrupt request signal <1> Communication error (IEERR) <2> Start interrupt (STARTF) <3> Status communication (STATUSF) <4> End of communication (ENDTRNS) <5> End of frame (ENDFRAM) <6>...
Page 547: Interrupt Source List
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.4.2 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850/SC2 can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified through software manipulation. The interrupt sources are listed below.
Page 548: Communication Error Cause Processing List
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.4.3 Communication error cause processing list The occurrence conditions for communication errors (timing errors, NACK reception errors, overrun errors, underrun errors, and parity errors), the internal IEBus controller error processing contents, and an example of processing by software are described below.
Page 549 CHAPTER 18 IEBus CONTROLLER (V850/SC2) Table 18-10. Communication Error Cause Processing List (2/2) Overrun Error Underrun Error Occurrence Local node During reception During transmission condition status Occurrence DR read is not executed by next data DR write is not executed by next data condition reception timing transmission timing...
Page 550: Interrupt Generation Timing And Main Cpu Processing
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.5 Interrupt Generation Timing and Main CPU Processing 18.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, master request, and slave reception).
Page 551 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (1) Slave reception processing If a slave reception request is confirmed during vector interrupt servicing, the data transfer direction of the macro service must change from RAM (memory) ‘ SFR (peripheral) to SFR (peripheral) ‘ RAM (memory) by the time the first data is received.
Page 552: Master Reception
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.5.2 Master reception Before performing master reception, it is necessary to notify the slave unit of slave transmission. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, set (1) the slave transmission enable flag (ENSLVTX), and waits. Initial preparation processing: Sets a unit address, slave address, and control data.
Page 553 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (1) Interrupt (INTIE1) occurrence If NACK is transmitted (hardware processing) in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted from the slave. If the receive data is not read by the time the next data is received, the hardware automatically transmits NACK.
Page 554: Slave Transmission
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.5.3 Slave transmission Initial preparation processing: Sets a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, slave transmission, and slave reception). Figure 18-19.
Page 555 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (1) Interrupt (INTIE1) occurrence If NACK is received from the master in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same data is retransmitted by hardware. If the transmit data is not written within the period of writing the next data, a communication error interrupt occurs due to the occurrence of an underrun, and communication ends abnormally.
Page 556: Slave Reception
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.5.4 Slave reception Initial preparation processing: Sets a unit address. Communication start processing: Sets the bus control register (enables communication, disables slave transmission, and enables slave reception). Figure 18-20. Slave Reception µ Approx. 1014 s (mode 1) <1>...
Page 557: Interval Of Occurrence Of Interrupt For Iebus Control
CHAPTER 18 IEBus CONTROLLER (V850/SC2) 18.5.5 Interval of occurrence of interrupt for IEBus control Each control interrupt must occur at each point of communication and perform the necessary processing by the time the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into consideration.
Page 558 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (2) Master reception Figure 18-22. Master Reception (Interval of Interrupt Occurrence) Broad- Telegraph Start bit Master address Slave address Control Data casting length Communication start Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 559 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (3) Slave transmission Figure 18-23. Slave Transmission (Interval of Interrupt Occurrence) Broad- Telegraph Start bit Master address Slave address Control Data casting length Communication start Communication Status request start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 560 CHAPTER 18 IEBus CONTROLLER (V850/SC2) (4) Slave reception Figure 18-24. Slave Reception (Interval of Interrupt Occurrence) Broad- Telegraph Start bit Master address Slave address Control Data casting length Communication start Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 561: Chapter 19 Fcan Controller (V850/Sc3)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) The V850/SC3 features an on-chip FCAN (Full Controller Area Network) controller that complies with CAN specification Ver. 2.0 PartB active. (The V850/SC3 product line includes the µ PD703089Y and µ PD70F3089Y as two-channel devices and the µ PD703088Y as a single-channel device.) 19.1 Features •...
Page 562: Configuration
19.3 Configuration FCAN is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface and a means of transmitting and receiving signals. (2) MAC (Memory Access Controller) This functional block controls access to the CAN module within the FCAN and to the CAN RAM.
Page 563 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-1. Block Diagram of FCAN Interrupt request INTCEn (NEC Peripheral I/O Bus) INTCRn INTCTn INTCME CAN bus FCAN controller CANTX1 CAN_H module 1 transceiver 1 CANRX1 CAN_L (Memory Access Controller) Note CANTX2 CAN_H interface...
Page 564: Internal Registers Of Fcan Controller
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.4 Internal Registers of FCAN Controller 19.4.1 Configuration of messages and buffers Table 19-2. Configuration of Messages and Buffers Address Register Name xx3FF800H to xx3FF81FH Message buffer 0 field xx3FF820H to xx3FF83FH Message buffer 1 field xx3FF840H to xx3FF85FH Message buffer 2 field xx3FF860H to xx3FF87FH...
Page 565: List Of Fcan Registers
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.4.2 List of FCAN registers (1/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF804H CAN message data length register 00 M_DLC00 Undefined √ xx3FF805H CAN message control register 00 M_CTRL00 √...
Page 566 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF84EH CAN message data register 026 M_DATA026 Undefined √ xx3FF84FH CAN message data register 027 M_DATA027 √ xx3FF850H CAN message ID register L02 M_IDL02 √...
Page 567 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (3/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF8AAH CAN message data register 052 M_DATA052 Undefined √ xx3FF8ABH CAN message data register 053 M_DATA053 √ xx3FF8ACH CAN message data register 054 M_DATA054 √...
Page 568 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (4/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF905H CAN message control register 08 M_CTRL08 Undefined √ xx3FF906H CAN message time stamp register 08 M_TIME08 √ xx3FF908H CAN message data register 080 M_DATA080 √...
Page 569 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (5/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF954H CAN message configuration register 10 M_CONF10 Undefined √ xx3FF955H CAN message status register 10 M_STAT10 √ xx3FF956H CAN status set/clear register 10 SC_STAT10 0000H √...
Page 570 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (6/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FF9AEH CAN message data register 136 M_DATA136 Undefined √ xx3FF9AFH CAN message data register 137 M_DATA137 xx3FF9B0H CAN message ID register L13 M_IDL13 xx3FF9B2H CAN message ID register H13...
Page 571 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (7/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFA0AH CAN message data register 162 M_DATA162 Undefined √ xx3FFA0BH CAN message data register 163 M_DATA163 √ xx3FFA0CH CAN message data register 164 M_DATA164 √...
Page 572 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (8/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFA65H CAN message control register 19 M_CTRL19 Undefined √ xx3FFA66H CAN message time stamp register 19 M_TIME19 √ xx3FFA68H CAN message data register 190 M_DATA190 √...
Page 573 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (9/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFAB4H CAN message configuration register 21 M_CONF21 Undefined √ xx3FFAB5H CAN message status register 21 M_STAT21 √ xx3FFAB6H CAN status set/clear register 21 SC_STAT21 0000H √...
Page 574 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (10/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFB0EH CAN message data register 246 M_DATA246 Undefined √ xx3FFB0FH CAN message data register 247 M_DATA247 √ xx3FFB10H CAN message ID register L24 M_IDL24 √...
Page 575 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (11/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFB6AH CAN message data register 272 M_DATA272 Undefined √ xx3FFB6BH CAN message data register 273 M_DATA273 √ xx3FFB6CH CAN message data register 274 M_DATA274 √...
Page 576 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (12/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFBC5H CAN message control register 30 M_CTRL30 Undefined √ xx3FFBC6H CAN message time stamp register 30 M_TIME30 √ xx3FFBC8H CAN message data register 300 M_DATA300 √...
Page 577 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (13/13) Address Function Register Name Symbol Bit Units for After Reset Manipulation Bits Bits √ xx3FFC40H CAN1 address mask 0 register L C1MASKL0 Undefined √ xx3FFC42H CAN1 address mask 0 register H C1MASKH0 √ xx3FFC44H CAN1 address mask 1 register L C1MASKL1 √...
Page 578: Control Registers
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5 Control Registers 19.5.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) The M_DLCn register sets the byte count in the data field of CAN message buffer n (n = 00 to 31). When receiving, the receive data field’s byte count is set (1).
Page 579: Can Message Control Registers 00 To 31 (M_Ctrl00 To M_Ctrl31)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.2 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) The M_CTRLn register is used to control operation of CAN message buffer n (n = 00 to 31). These registers can be read/written in 8-bit units. (1/2) After reset: Undefined Address: See Table 19-4...
Page 580 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/2) Specifies the enable/disable setting for interrupt requests Interrupt requests disabled Interrupt requests enabled • An interrupt request occurs when the IE bit is 1 under the following conditions. • When a message is sent from the transmit message buffer •...
Page 581: Can Message Time Stamp Registers 00 To 31 (M_Time00 To M_Time31)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-4. Addresses of M_CTRLn (n = 00 to 31) Register Name Address Register Name Address M_CTRL00 xx3FF805H M_CTRL16 xx3FFA05H M_CTRL01 xx3FF825H M_CTRL17 xx3FFA25H M_CTRL02 xx3FF845H M_CTRL18 xx3FFA45H M_CTRL03 xx3FF865H M_CTRL19 xx3FFA65H M_CTRL04 xx3FF885H M_CTRL20 xx3FFA85H M_CTRL05 xx3FF8A5H...
Page 582 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-5. Addresses of M_TIMEn (n = 00 to 31) Register Name Address Register Name Address M_TIME00 xx3FF806H M_TIME16 xx3FFA06H M_TIME01 xx3FF826H M_TIME17 xx3FFA26H M_TIME02 xx3FF846H M_TIME18 xx3FFA46H M_TIME03 xx3FF866H M_TIME19 xx3FFA66H M_TIME04 xx3FF886H M_TIME20 xx3FFA86H M_TIME05 xx3FF8A6H...
Page 583: Can Message Data Registers N0 To N7 (M_Datan0 To M_Datan7)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.4 CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) The M_DATAn0 to M_DATAn7 registers are areas where up to 8 bytes of transmit or receive message data is stored. These registers can be read/written in 8-bit units. The M_DATAn0 to M_DATAn7 registers are used to hold receive message data and transmit message data.
Page 584 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-6. Addresses of M_DATAnx (n = 00 to 31, x = 0 to 7) Register M_DATAn0 M_DATAn1 M_DATAn2 M_DATAn3 M_DATAn4 M_DATAn5 M_DATAn6 M_DATAn7 Name xx3FF808H xx3FF809H xx3FF80AH xx3FF80BH xx3FF80CH xx3FF80DH xx3FF80EH xx3FF80FH xx3FF828H xx3FF829H xx3FF82AH xx3FF82BH xx3FF82CH...
Page 585: Can Message Id Registers L00 To L31 And H00 To H31
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.5 CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) The M_IDLn and M_IDHn registers are areas used to set identifiers (n = 00 to 31). These registers can be read/written in 16-bit units.
Page 586 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-7. Addresses of M_IDLn and M_IDHn (n = 00 to 31) Register Name Address Register Name Address M_IDL00 xx3FF810H M_IDL16 xx3FFA10H M_IDH00 xx3FF812H M_IDH16 xx3FFA12H M_IDL01 xx3FF830H M_IDL17 xx3FFA30H M_IDH01 xx3FF832H M_IDH17 xx3FFA32H M_IDL02 xx3FF850H M_IDL18 xx3FFA50H...
Page 587: Can Message Configuration Registers 00 To 31 (M_Conf00 To M_Conf31)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.6 CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFn register is used to specify the message buffer type and mask setting (n = 00 to 31). These registers can be read/written in 8-bit units. After reset: Undefined Address: See Table 19-8 M_CONFn...
Page 588 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-8. Addresses of M_CONFn (n = 00 to 31) Register Name Address Register Name Address M_CONF00 xx3FF814H M_CONF16 xx3FFA14H M_CONF01 xx3FF834H M_CONF17 xx3FFA34H M_CONF02 xx3FF854H M_CONF18 xx3FFA54H M_CONF03 xx3FF874H M_CONF19 xx3FFA74H M_CONF04 xx3FF894H M_CONF20 xx3FFA94H M_CONF05 xx3FF8B4H...
Page 589: Can Message Status Registers 00 To 31 (M_Stat00 To M_Stat31)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). These registers are read-only, in 8-bit units. Cautions 1.
Page 590 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-9. Addresses of M_STATn (n = 00 to 31) Register Name Address Register Name Address M_STAT00 xx3FF815H M_STAT16 xx3FFA15H M_STAT01 xx3FF835H M_STAT17 xx3FFA35H M_STAT02 xx3FF855H M_STAT18 xx3FFA55H M_STAT03 xx3FF875H M_STAT19 xx3FFA75H M_STAT04 xx3FF895H M_STAT20 xx3FFA95H M_STAT05 xx3FF8B5H...
Page 591: Can Status Set/Clear Registers 00 To 31 (Sc_Stat00 To Sc_Stat31)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.8 CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31) The SC_STATn register is used to set/clear the transmit/receive status information (n = 00 to 31). These registers are write-only, in 16-bit units. After reset: 0000H Address: See Table 19-10 SC_STATn set DN...
Page 592 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-10. Addresses of SC_STATn (n = 00 to 31) Register name Address Register name Address SC_STAT00 xx3FF816H SC_STAT16 xx3FFA16H SC_STAT01 xx3FF836H SC_STAT17 xx3FFA36H SC_STAT02 xx3FF856H SC_STAT18 xx3FFA56H SC_STAT03 xx3FF876H SC_STAT19 xx3FFA76H SC_STAT04 xx3FF896H SC_STAT20 xx3FFA96H SC_STAT05 xx3FF8B6H...
Page 593: Can Interrupt Pending Register (Ccintp)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.9 CAN interrupt pending register (CCINTP) The CCINTP register is used to confirm the pending status of various interrupts. This register is read-only in 16-bit units. After reset: 0000H Address: xx3FFC04H CCINTP INTMAC CAN2ERR CAN2REC CAN2TRX CAN1ERR CAN1REC CAN1TRX Note 1 INTMAC Pending status of MAC error...
Page 594 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Notes 1. MAC (Memory Access Control) errors are errors that are set only when an interrupt source has occurred for the CAN global interrupt pending register (CGINTP). 2. µ PD703089Y and 70F3089Y only Remark GINT2, GINT1: Bits 2 and 1 of the CAN global interrupt pending register (CGINTP) CnINT6 to CnINT0: Bits 6 to 0 of the CANn interrupt pending register (CnINTP)
Page 595: Can Global Interrupt Pending Register (Cgintp)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.10 CAN global interrupt pending register (CGINTP) The CGINTP register is used to confirm the pending status of MAC access error interrupts. This register can be read/written in 8-bit or 16-bit units. Cautions 1. When “1” is written to a bit in the CGINTP register, that bit is cleared (0). When “0” is written to it, the bit’s value does not change.
Page 596: Cann Interrupt Pending Register (Cnintp)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.11 CANn interrupt pending register (CnINTP) The CnINTP register is used to confirm the pending status of interrupts issued to the FCAN. This register can be read/written in 8-bit or 16-bit units. The CAN2 interrupt pending register (C2INTP) is valid only in models µ PD703089Y and 70F3089Y. Cautions 1.
Page 597 CHAPTER 19 FCAN CONTROLLER (V850/SC3) After reset: 0000H Addresses: C1INTP: xx3FFC22H C2INTP: xx3FFC24H CnINTP (n = 1, 2) CnINT6 CnINT5 CnINT4 CnINT3 CnINT2 CnINT1 CnINT0 CnINT6 Pending status of CAN module error interrupt Not pending Pending CnINT5 Pending status of CAN bus error interrupt Not pending Pending CnINT4...
Page 598: Can Stop Register (Cstop)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.12 CAN stop register (CSTOP) The CSTOP register controls clock supply to the entire CAN system. This register can be read/written in 16-bit units. Cautions 1. Be sure to set the CSTP bit (1) if the FCAN function will not be used. 2.
Page 599: Can Global Status Register (Cgst)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.13 CAN global status register (CGST) The CGST register indicates global status information. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 Cautions Regarding Bit Set/Clear Function.
Page 600 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/2) (a) Read Status of global operation mode Note 1 CAN module is reset and access to CAN module register is prohibited Note 1 CAN module operation is enabled and access to CAN module register enabled •...
Page 601 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (b) Write set EFSD clear EFSD EFSD bit setting EFSD bit cleared (0) EFSD bit set (1) Other than above No change in EFSD bit’s value set TSM clear TSM TSM bit setting TSM bit cleared (0) TSM bit set (1) Other than above No change in TSM bit’s value...
Page 602: Can Global Interrupt Enable Register (Cgie)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.14 CAN global interrupt enable register (CGIE) The CGIE register is used to issue interrupt requests for global interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 19.6 Cautions Regarding Bit Set/Clear Function.
Page 603: Can Main Clock Select Register (Cgcs)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.15 CAN main clock select register (CGCS) The CGCS register is used to select the CAN main clock. This register can be read/written in 16-bit units. Caution When the GOM bit of the CGST register is 1, write accessing the CGCS register is prohibited. After reset: 7F05H Address: xx3FFC14H CGCS...
Page 604 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-2. FCAN Clocks CAN main clock select register (CGCS) CGTS7 CGTS6 CGTS5 CGTS4 CGTS3 CGTS2 CGTS1 CGTS0 GTCS1 GTCS0 MCP3 MCP2 MCP1 MCP0 MEM1 GTS1 Global timer Global timer Prescaler Time stamp counter clock prescaler system clock CANn synchronization control register...
Page 605: Can Time Stamp Count Register (Cgtsc)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.16 CAN time stamp count register (CGTSC) The CGTSC register indicates the contents of the time stamp counter. This register can be read at any time. This register can be written to only when clearing bits. The clear function writes 0 to all bits in the CGTSC register.
Page 606: Can Message Search Start/Result Register (Cgmss/Cgmsr)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.17 CAN message search start/result register (CGMSS/CGMSR) The CGMSS/CGMSR register indicates the message search start/result status. Messages in the message buffer that match the specified search criteria can be searched quickly. These registers can be read/written in 16-bit units. Cautions 1.
Page 607 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/2) (b) Write CTRQ Transmit request and message ready flag check Transmit request and message ready flags not checked Transmit request and message ready flags checked CMSK Message check Checked regardless of mask setting Only unmasked messages checked Status check of M_STATn register’s DN flag (n = 00 to 31) Status of M_STATn register’s DN flag not checked Status of M_STATn register’s DN flag checked...
Page 608: Cann Address Mask A Registers L And H (Cnmaskla And Cnmaskha)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) The CnMASKLa and CnMASKHa registers are used to extend the number of receivable messages by masking part of the message’s identifier (ID) and then ignoring the masked parts (a = 0 to 3, n = 1, 2). These registers can be read/written in 16-bit units.
Page 609 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Table 19-11. Addresses of CnMASKLa and CnMASKHa (a = 0 to 3, n = 1, 2) Register Name Address Register Name Address C1MASKL0 xx3FFC40H C2MASKL0 xx3FFC80H C1MASKH0 xx3FFC42H C2MASKH0 xx3FFC82H C1MASKL1 xx3FFC44H C2MASKL1 xx3FFC84H C1MASKH1 xx3FFC46H C2MASKH1 xx3FFC86H...
Page 610: Cann Control Register (Cnctrl)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.19 CANn control register (CnCTRL) The CnCTRL register is used to control the operation of the CAN module. This register can be read/written in 16-bit units. The C2CTRL register is valid only in models µ PD703089Y and 70F3089Y. Cautions 1.
Page 611 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/4) (a) Read TSTAT Transmit status flag Transmit stop status Transmit operating status RSTAT Receive status flag Receive stop status Receive operating status ISTAT Initialization status flag Normal operating status FCAN is stopped and initialized •...
Page 612 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (3/4) (a) Read STOP CAN stop mode control bit Normal CAN sleep mode CAN stop mode (change in CAN bus does not cause wakeup) • CAN stop mode can be selected only when the CAN module has been set to CAN sleep mode, i.e., when the SLEEP bit has been set (1).
Page 613 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (4/4) (b) Write clear DLEVR bit setting DLEVR DLEVR DLEVR bit cleared (0) DLEVR bit set (1) Other than above DLEVR bit not changed clear DLEVT bit setting DLEVT DLEVT DLEVT bit cleared (0) DLEVT bit set (1) Other than above DLEVT bit not changed clear...
Page 614: Cann Definition Register (Cndef)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.20 CANn definition register (CnDEF) The CnDEF register is used to define the operation of the CAN module. This register can be read/written in 16-bit units. The C2DEF register is valid only in models µ PD703089Y and 70F3089Y. Cautions 1.
Page 615 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/4) (a) Read Specification of CAN module’s operating mode Normal operating mode Diagnostic processing mode • When in diagnostic processing mode (MOM bit = 1), the CnBRP register can be accessed only when the CAN module has been set to initialization mode (i.e., when the CnCTRL register’s ISTAT bit = INIT bit = 1).
Page 616 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (3/4) (a) Read WAKE CAN sleep mode cancellation status Normal operation Cancel CAN sleep mode • The WAKE bit is set (1) only when the CAN sleep mode is released due to a change of CAN bus and an error interrupt occurs.
Page 617 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (4/4) (b) Write set DGM clear DGM DGM bit setting DGM bit cleared (0) DGM bit set (1) Other than above DGM bit not changed set MOM clear MOM MOM bit setting MOM bit cleared (0) MOM bit set (1) Other than above MOM bit not changed...
Page 618: Cann Information Register (Cnlast)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.21 CANn information register (CnLAST) The CnLAST register indicates the CANn module’s error information and the number of the message buffer received last. This register is read-only, in 16-bit units. The C2LAST register is valid only in models µ PD703089Y and 70F3089Y. After reset: 00FFH Addresses: C1LAST: xx3FFC54H C2LAST: xx3FFC94H...
Page 619: Cann Error Count Register (Cnerc)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.22 CANn error count register (CnERC) The CnERC register indicates the count values of the transmission/reception error counters. This register is read-only in 16-bit units. The C2ERC register is valid only in models µ PD703089Y and 70F3089Y. After reset: 0000H Addresses: C1ERC: xx3FFC56H C2ERC: xx3FFC96H...
Page 620: Cann Interrupt Enable Register (Cnie)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.23 CANn interrupt enable register (CnIE) The CnIE register is used to enable/disable the CAN module’s interrupts. This register can be read/written in 16-bit units. The C2IE register is valid only in models µ PD703089Y and 70F3089Y. Cautions 1.
Page 621 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/3) (a) Read E_INT2 CAN transmit error passive or bus off interrupt enable flag Interrupt disabled Interrupt enabled E_INT1 CAN receive completion interrupt enable flag Interrupt disabled Interrupt enabled • When IE bit of the M_CTRLn register is 1, a reception completion interrupt occurs regardless of the setting of the E_INT1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (RMDE0 bit of the M_CTRLn register = 0).
Page 622 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (3/3) (b) Write set E_INT6 clear E_INT6 E_INT6 bit setting E_INT6 interrupt cleared (0) E_INT6 interrupt set (1) Other than above E_INT6 interrupt not changed set E_INT5 clear E_INT5 E_INT5 bit setting E_INT5 interrupt cleared (0) E_INT5 interrupt set (1) Other than above E_INT5 interrupt not changed...
Page 623: Cann Bus Active Register (Cnba)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.24 CANn bus active register (CnBA) The CnBA register indicates frame information output via the CAN bus. This register is read-only, in 16-bit units. The C2BA register is valid only in models µ PD703089Y and 70F3089Y. After reset: 00FFH Addresses: C1BA: xx3FFC5AH C2BA: xx3FFC9AH...
Page 624: Cann Bit Rate Prescaler Register (Cnbrp)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.25 CANn bit rate prescaler register (CnBRP) The CnBRP register is used to set the transmission baud rate for the CAN module. Use the CnBRP register to select the CAN protocol layer basic system clock (f ).
Page 625 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (1/2) After reset: 0000H Addresses: C1BRP: xx3FFC5CH C2BRP: xx3FFC9CH (a) When TLM = 0 CnBRP (n = 1, 2) BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 (b) When TLM = 1 CnBRP BTYPE (n = 1, 2) BRP7 BRP6 BRP5...
Page 626 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/2) (b) When TLM = 1 Transfer layer mode specification 8-bit prescaler mode BTYPE CAN bus type specification Low speed (≤ 125 Kbps) High speed (> 125 Kbps) BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer basic system clock...
Page 627: Cann Bus Diagnostic Information Register (Cndinf)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.26 CANn bus diagnostic information register (CnDINF) The CnDINF register indicates all the CAN bus bits, including the stuff bits and delimiters. This information is used only for diagnostic purposes. This register is read-only in 16-bit units. The C2DINF register is valid only in models µ...
Page 628: Cann Synchronization Control Register (Cnsync)
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.5.27 CANn synchronization control register (CnSYNC) The CnSYNC register controls the data bit time for transmission speed. This register can be read/written in 16-bit units. The C2SYNC register is valid only in models µ PD703089Y and 70F3089Y. Cautions 1.
Page 629 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2/2) SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 Position of sampling point BTL × 3 Note BTL × 4 Note BTL × 5 BTL × 6 BTL × 7 BTL × 8 BTL × 9 BTL × 10 BTL ×...
Page 630: Cautions Regarding Bit Set/Clear Function
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.6 Cautions Regarding Bit Set/Clear Function The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them.
Page 631 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-4. 16-Bit Data During Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Status of bit n after bit set/clear operation...
Page 632: Time Stamp Function
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.7 Time Stamp Function Caution In V850/SC3, time stamp function detection during message transmission/reception cannot be used. Only the time stamp function by EOF detection during message reception can be used for the V850/SC3. However, only the value captured by the M_TIME register is valid when the TSM bit of the CGST register is set to 1 and the TMR bit of the CnCTRL register is set to 1.
Page 633 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-6. Time Stamp Function Setting for Message Reception (When CxCTRL Register’s TMR Bit = 1) ACK field Message CAN message buffer n <1> Time stamp M_TIMEn counter <Explanation> <1> When the EOF is sent via the CAN bus (a valid message is acknowledged), the captured time stamp counter value is copied to the M_TIMEn register in CAN message buffer n when a message is stored in CAN message buffer n.
Page 634 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-7. Time Stamp Function Setting for Message Transmission (When M_CTRL Register’s ATS Bit = 1) ACK field Message <2> <1> Time stamp Temporary counter buffer <Explanation> <1> The time stamp counter value is captured to the temporary buffer when the SOF is detected on the CAN bus. Note <2>...
Page 635: Message Processing
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.8 Message Processing A modular system is used for the FCAN controller. Consequently, messages can be placed at any location within the message area. The messages can be linked to mask functions that are in turn linked to CAN modules. User’s Manual U15109EJ3V0UD...
Page 636: Message Transmission
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.8.1 Message transmission The FCAN system is a multiplexed communication system. The priority of message transmission within this system is determined based on message identifiers (IDs). To facilitate communication processing by application software when there are several messages awaiting transmission, the CAN module uses hardware to check the message IDs and automatically determine whether or not linked messages are prioritized.
Page 637: Message Reception
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.8.2 Message reception When two or more message buffers of the CAN module receive a message, the storage priority of the received messages is as follows (the storage priority differs between data frames and remote frames). Table 19-13.
Page 638: Mask Function
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.9 Mask Function A mask linkage function can be defined for each received message. This means that there is no need to distinguish between local masks and global masks. When the mask function is used, the received message’s identifier is compared with the message buffer’s identifier and the message can be stored in the defined message buffer regardless of whether the mask sets “0”...
Page 639 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <3> Mask setting for CAN module 1 (mask 1) (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13...
Page 640: Protocol
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.10 Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed in the ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 641: Frame Types
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.10.2 Frame types Following four types of frames are used in CAN protocol. Frame Type Table 19-16. Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 642 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (2) Remote frame A remote frame is composed of six fields. Figure 19-12. Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1.
Page 643 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <2> Arbitration field The arbitration field is used to set the priority, data frame or remote frame, and frame format. Figure 19-14. Arbitration Field (During Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 644 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). Figure 19-16. Control Field (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE)
Page 645 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <4> Data field The data field contains the amount of data (byte unit) set by the control field. Up to 8 units of data can be set. Figure 19-17. Data Field (Control field) Data field (CRC field) Data Data...
Page 646 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <6> ACK field The ACK field is used to confirm normal reception. Figure 19-19. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark D: Dominant = 0 R: Recessive = 1 •...
Page 647 CHAPTER 19 FCAN CONTROLLER (V850/SC3) <8> Interframe space The interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next. • The bus status differs depending on the error status. (a) Error active node The error active node is composed of a 3-bit intermission field and a bus idle field.
Page 648 CHAPTER 19 FCAN CONTROLLER (V850/SC3) • Operation in error status Table 19-20. Operation in Error Status Error Status Operation Error active When the bus is idle, the transmit enable mode is set for each node. Transmission then starts from a node. Error passive After the 8-bit bus idle field (suspend transmission), the transmit enable mode is set.
Page 649: Error Frame
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.10.4 Error frame An error frame is output from a node in which an error has been detected. Figure 19-23. Error Frame Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter...
Page 650: Overload Frame
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.10.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node is not yet ready to receive. • If a dominant level is detected at the first two bits during intermission mode. •...
Page 651: Functions
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.11 Functions 19.11.1 Determination of bus priority (1) When one node has starting transmitting • In bus idle mode, the node that outputs data first starts transmitting. (2) When several nodes have started transmitting • The node that outputs the longest string of consecutive dominant-level bits starting from the first bit in the arbitration field has top priority for bus access (dominant-level bits take precedence due to wired-OR bus arbitration).
Page 652: Can Sleep Mode/Can Stop Mode Function
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.11.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function can be used to set the FCAN controller to sleep (standby) mode to reduce power consumption. The CAN sleep mode is set via the procedure stipulated in the CAN specifications. The CAN sleep mode can be set to either wake up or not wake up when the bus is operated (this is controlled via CPU access).
Page 653 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (4) Error statuses (a) Types of error statuses The three types of error statuses are listed below. Error active Error passive Bus off • The error status is controlled by the transmit error counter and receive error counter (see 19.5.22 CANn error count register (CnERC)).
Page 654 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (b) Error counter The error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. The count up/count down timing occurs at the first bit of the error delimiter.
Page 655: Baud Rate Control Function
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.11.7 Baud rate control function (1) Prescaler The FCAN controller of the V850/SC3 includes a prescaler for dividing the clock supplied to the CAN (f MEM1 This prescaler generates a clock (f ) that is based on a division ratio ranging from 2 to 128 applied to the CAN base clock (f ) when the CnBRP register’s TLM bit = 0, and from 2 to 256 when the TLM bit = 1 (see 19.5.25 CANn bit rate prescaler register (CnBRP)).
Page 656 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-25. Nominal Bit Time Nominal bit time Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point Segment name Segment length Description Sync segment This segment begins when resynchronization occurs. (Synchronization Segment) Prop segment 1 to 8 (programmable) This segment is used to absorb the delays caused by...
Page 657 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-26. Coordination of Data Bit Synchronization Bus idle Start of frame CAN bus Sync Prop Phase Phase Bit timing segment segment segment 1 segment 2 (b) Resynchronization Resynchronization is performed when a level change is detected on the bus during a receive operation (only when the last sampling was the recessive level).
Page 658: Operations
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.12 Operations 19.12.1 Initialization processing Figure 19-28 shows a flowchart of initialization processing. The register setting flow is shown in Figures 19-29 to 19-41. Figure 19-28. Initialization Processing START CSTP = 1? (CSTOP) CSTP = 0 (CSTOP) Set CAN main clock selection register : See setting shown in Figure 19-29 CAN Main Clock Selection Register (CGCS) Settings (CGCS)
Page 659 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-29. Setting of CAN Main Clock Select Register (CGCS) START Select clock for memory access controller / (n + 1) MEM1 (MCP0 to MCP3) n = 0 to 15 (set using bits MCP0 to MCP3) GTCS1, GTCS0 = 00: f GTS1 Select global timer clock...
Page 660 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-31. Setting of CAN Global Status Register (CGST) START Start FCAN operation set GOM = 1 clear GOM = 0 Use time stamp function? set TSM = 1 clear TSM = 0 Figure 19-32. Setting of CANn Bit Rate Prescaler (CnBRP) START Transfer speed is 125 Kbps or less...
Page 661 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-33. Setting of CANn Synchronization Control Register (CnSYNC) START 1 bit time = BTL × (m + 1) Set data bit time (DBTR4 to DBTR0) m = 7 to 24 (set using bits DBTR4 to DBTR0) Sample point = BTL ×...
Page 662 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-34. Setting of CANn Interrupt Enable Register (CnIE) START Interrupt enable flag Enable interrupt for end of transmission for E_INT0? clear E_INT0 = 1 set E_INT0 = 1 set E_INT0 = 0 clear E_INT0 = 0 Interrupt enable flag Enable interrupt for end of reception...
Page 663 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-35. Setting of CANn Definition Register (CnDEF) START Set to diagnostic processing mode? clear MOM = 1 set MOM = 1 Normal operating mode Diagnostic processing mode set MOM = 0 clear MOM = 0 Store to buffer used for Note diagnostic processing mode...
Page 664 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-36. Setting of CANn Control Register (CnCTRL) START Set time stamp for Store timer value at SOF? receiving Store timer value at EOF clear TMR = 1 set TMR = 1 set TMR = 0 clear TMR = 0 Set overwrite for receive Store message...
Page 665 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-37. Setting of CANn Address Mask a Registers L and H (CnMASKLa and CnMASKHa) START Standard frame (y = 0 to 17) CMIDy = 1 Mask setting for extended frame Mask setting for standard frame (x = 0 to 28) (x = 18 to 28) Compare with received...
Page 666 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-38. Message Buffer Setting START Set message Standard frame? ID type IDE = 0 (standard) IDE = 1 (extended) (M_IDHm) (M_IDHm) Set identifier (standard, extended) See Figure 19-39 Setting of CAN Message Set message configuration Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Set message length...
Page 667 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-39. Setting of CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) START Release CAN Use message buffer? message buffer MA2 to MA0 = 000 CAN module 1 Message buffer address specification CAN module 2 MA2 to MA0 = 010 MA2 to MA0 = 001 MT2 to MT0 = 000...
Page 668 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-40. Setting of CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) START Transmit/receive data frame? RTR = 0 RTR = 1 Transmit/receive remote frame Disable interrupt? IE = 0 IE = 1 Enable interrupt Remote frame auto Set remote frame auto...
Page 669 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-41. Setting of CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) START Clear DN flag clear DN = 1, set DN = 0 (SC_STATm) Clear TRQ flag clear TRQ = 1, set TRQ = 0 (SC_STATm) Clear RDY flag clear RDY = 1, set RDY = 0...
Page 670: Transmit Setting
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.12.2 Transmit setting Transmit messages are output from the target message buffer. Figure 19-42. Transmit Setting START Select transmit message buffer Set data (M_DATAmn) Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATm) Set transmit request flag set TRQ = 1, clear TRQ = 0...
Page 671: Receive Setting
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.12.3 Receive setting Receive messages are retrieved from the target message buffer. Figure 19-43. Setting of Receive Operation Using Reception Completion Interrupt START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATm) Reception completion interrupt occurs : Detection methods...
Page 672 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-44. Setting Receive Operation Using Reception Polling START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATm) CnINT1 = 1 (CnINTP) : Detection methods Detect target message <1> Detect using CANn information register (CnLAST) buffer <2>...
Page 673 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-45. Setting of CAN Message Search Start/Result Register (CGMSS/CGMSR) START Check DN flag (CDN = 1) Check masked messages? Search non mask- CMSK = 0 Search all messages CMSK = 1 linked messages only (CGMSS) (regardless of mask setting) (CGMSS)
Page 674: Can Sleep Mode
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.12.4 CAN sleep mode In CAN sleep mode, the FCAN controller can be set to standby mode. A wakeup occurs when there is a bus operation. Figure 19-46. CAN Sleep Mode Setting START set SLEEP = 1 clear SLEEP = 0 (CnCTRL) SLEEP = 1...
Page 675 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-48. Clearing CAN Sleep Mode by CPU START clear SLEEP = 1 set SLEEP = 0 (CnCTRL) SLEEP = 0 (CnCTRL) End of CAN sleep mode clearing operation Remark n = 1, 2 User’s Manual U15109EJ3V0UD...
Page 676: Can Stop Mode
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.12.5 CAN stop mode In CAN stop mode, the FCAN controller can be set to standby mode. No wakeup occurs when there is a bus operation (stop mode is controlled by CPU access only). Figure 19-49. CAN Stop Mode Setting START SLEEP = 1 (CnCTRL)
Page 677: Rules For Correct Setting Of Baud Rate
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.13 Rules for Correct Setting of Baud Rate The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that settings are within the range of limit values.
Page 678 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Given the above limit values, the following four settings are possible. Prescaler SPT (MAX.) Calculated SPT 5/8 = 62.5% 9/12 = 75% 13/16 = 81% 17/24 = 71% 16 MHz/83 Kbps ≅ 192 = 64 × 3 <1>...
Page 679 CHAPTER 19 FCAN CONTROLLER (V850/SC3) (ii) DBT (data bit time) setting DBT is calculated as shown below. • DBT = BTL × (a + 1) : [7 ≤ a ≤ 24] Value a is set using bits 4 to 0 (DBTR4 to DBTR0) of the CnSYNC register. DBT = BTL ×...
Page 680 CHAPTER 19 FCAN CONTROLLER (V850/SC3) Figure 19-51. CnSYNC Register Settings CnSYNC SAMP SJWR1 SJWR0 SPTR4 SPTR3 Setting SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 Setting User’s Manual U15109EJ3V0UD...
Page 681: Ensuring Data Consistency
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.14 Ensuring Data Consistency When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent. Two methods are used to ensure data consistency: sequential data read and burst read mode. 19.14.1 Sequential data read When the CPU performs sequential access of a message buffer, data is read from the buffer in the order shown in Figure 19-74 below.
Page 682: Burst Read Mode
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.14.2 Burst read mode Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the synchronization of data. Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied from the message buffer area to a temporary read buffer.
Page 683: Interrupt Conditions
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.15 Interrupt Conditions 19.15.1 Interrupts that occur for FCAN controller When interrupts are enabled (condition <1>: the M_CTRLm register’s IE bit = 1, conditions other than <1>: C_IE register’s interrupt flags = 1), interrupts will occur under the following conditions (m = 00 to 31). <1>...
Page 684: How To Shutdown Fcan Controller
CHAPTER 19 FCAN CONTROLLER (V850/SC3) 19.16 How to Shutdown FCAN Controller The following procedure should be used to stop CAN bus operations in order to stop the clock supply to the CAN interface (to set low power mode). <1> Set FCAN controller initialization mode •...
Page 685 CHAPTER 19 FCAN CONTROLLER (V850/SC3) [When CAN communication is performed by polling of bits, not using interrupt routines] • The following interrupt mask flags and interrupt enable bits are used when set (1) (do not clear (0) them). • CANMKn bit of CANICn register (n= 1 to 7) •...
Page 686: Chapter 20 Electrical Specifications
CHAPTER 20 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Supply voltage pin = V –0.3 to +6.0 ADCV ADCV pin = V –0.3 to +6.0 pin ≤ PORTV pin ≤ PORTV PORTV PORTV –0.3 to V Note 1 Input voltage PORTV...
Page 687 CHAPTER 20 ELECTRICAL SPECIFICATIONS Operating Conditions ≤ ≤ ≤ ≤ PORTV ≤ ≤ ≤ ≤ PORTV ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ V ≤ ≤ ≤ ≤ ADCV (1) Operating voltage (PORTV Parameter Symbol Conditions MIN. TYP. MAX.
Page 688 CHAPTER 20 ELECTRICAL SPECIFICATIONS Recommended Oscillator (1) Main clock oscillator (T = –40 to +85°C) (a) Connection of ceramic resonator or crystal resonator Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency Oscillation stabilization time – When reset is released –...
Page 689 CHAPTER 20 ELECTRICAL SPECIFICATIONS (2) Subclock oscillator (T = –40 to +85°C) (a) Connection of crystal resonator Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency 32.768 Oscillation stabilization time – When reset is released Cautions 1. Subclock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited.
Page 690 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, PORTV = PORTV = PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = ADCV = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = ADCV = 4.0 to 5.5 V) (1/2) Parameter...
Page 691 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, PORTV = PORTV = PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = ADCV = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = ADCV = 4.0 to 5.5 V) (2/2) Parameter...
Page 692 CHAPTER 20 ELECTRICAL SPECIFICATIONS Data Retention Characteristics (T = –40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Data retention voltage STOP mode (no functions operating) DDDR µ A Note Data retention current STOP mode (no functions operating) DDDR µ...
Page 693 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Test Points (V , PORTV Test points Input signal AC Test Output Test Points (V , PORTV Output signal Test points Load Conditions (Device under test) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, lower the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 694 CHAPTER 20 ELECTRICAL SPECIFICATIONS (1) Clock timing (a) T = –40 to +85°C, V = 4.0 to 5.5 V, PORTV = 4.0 to 5.5 V, PORTGND = 0 V Parameter Symbol Conditions MIN. MAX. Unit 31 µ s CLKOUT output cycle <1>...
Page 695 CHAPTER 20 ELECTRICAL SPECIFICATIONS (2) Output waveform (other than CLKOUT) (a) T = –40 to +85°C, V = 4.0 to 5.5 V, PORTV = 4.0 to 5.5 V, PORTGND = 0 V Parameter Symbol Conditions MIN. MAX. Unit Output rise time <6>...
Page 696 CHAPTER 20 ELECTRICAL SPECIFICATIONS (4) Bus timing (a) Clock asynchronous (T = –40 to +85°C, V = 4.0 to 5.5 V, PORTV = 4.0 to 5.5 V) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) <10> 0.5T – 20 SAST Address hold time (from ASTB↓) <11>...
Page 697 CHAPTER 20 ELECTRICAL SPECIFICATIONS (b) Clock asynchronous = –40 to +85°C, PORTV = 3.0 to 4.0 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) Parameter Symbol Conditions...
Page 698 CHAPTER 20 ELECTRICAL SPECIFICATIONS (c) Clock synchronous (T = –40 to +85°C, V = 4.0 to 5.5 V, PORTV = 4.0 to 5.5 V) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT↑ to address <39> Delay time from CLKOUT↑ to address float <40>...
Page 699 CHAPTER 20 ELECTRICAL SPECIFICATIONS (e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <39> A16 to A21 (output) Note (output) < 43 > < 44 > < 13 > < 40 > Address Data AD0 to AD15 (I/O) < 41 > <...
Page 700 CHAPTER 20 ELECTRICAL SPECIFICATIONS (f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <39> A16 to A21 (output) Note (output) < 45 > AD0 to AD15 (I/O) Address Data < 41 > < 10 > < 11 > < 41 > ASTB (output) <...
Page 701 CHAPTER 20 ELECTRICAL SPECIFICATIONS (g) Bus hold timing CLKOUT (output) < 48 > < 48 > < 49 > <34> HLDRQ (input) < 51 > < 51 > < 38 > < 37 > HLDAK (output) <35> <50> <36> A16 to A19 (output) Note (output) AD0 to AD15 (I/O)
Page 702 CHAPTER 20 ELECTRICAL SPECIFICATIONS (5) Interrupt timing = –40 to +85°C, PORTV = 3.0 to 5.0 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) Parameter Symbol Conditions...
Page 703 CHAPTER 20 ELECTRICAL SPECIFICATIONS (6) TIn timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) Parameter Symbol Conditions...
Page 704 CHAPTER 20 ELECTRICAL SPECIFICATIONS (7) Asynchronous serial interface (UART0 to UART3) timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) Parameter Symbol...
Page 705 CHAPTER 20 ELECTRICAL SPECIFICATIONS (8) 3-wire serial interface (CSI0, CSI2, CSI3) timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) (a) Master mode Parameter...
Page 706 CHAPTER 20 ELECTRICAL SPECIFICATIONS <63> <64> <65> SCKn (I/O) <66> <67> SIn (input) Input data <68> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 2, 3 User’s Manual U15109EJ3V0UD...
Page 707 CHAPTER 20 ELECTRICAL SPECIFICATIONS (9) 3-wire variable-length serial interface (CSI4) timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) (a) Master mode Parameter...
Page 708 CHAPTER 20 ELECTRICAL SPECIFICATIONS <69> <70> <71> SCK4 (I/O) <72> <73> SI4 (input) Input data <74> SO4 (output) Output data Remark Broken lines indicate high impedance. User’s Manual U15109EJ3V0UD...
Page 709 CHAPTER 20 ELECTRICAL SPECIFICATIONS (10) 3-wire serial interface (CSI5, CSI6) timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) (a) Master mode Parameter...
Page 710 CHAPTER 20 ELECTRICAL SPECIFICATIONS <75> <76> <77> SCKn (I/O) <78> <79> SIn (input) Input data <80> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 5, 6 User’s Manual U15109EJ3V0UD...
Page 711 CHAPTER 20 ELECTRICAL SPECIFICATIONS (11) I C interface (I C0, I C1) timing = –40 to +85°C, PORTV = 3.0 to 5.5 V, µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V = 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V = 4.0 to 5.5 V) Parameter Symbol...
Page 712 CHAPTER 20 ELECTRICAL SPECIFICATIONS <83> <84> SCLn (I/O) <85> <89> <88> <86> <87> <82> <91> <90> <82> SDAn (I/O) <81> Stop Start Restart Stop <89> <88> condition condition condition condition Remark n = 0, 1 A/D Converter Characteristics (T = –40 to +85°C, V = ADCV = 4.5 to 5.5 V, GND = ADCGND = 0 V) Parameter...
Page 713 CHAPTER 20 ELECTRICAL SPECIFICATIONS Flash Memory Programming Mode ( µ µ µ µ PD70F3089Y only) Basic Characteristics (T = –20 to +85°) Parameter Symbol Conditions MIN. TYP. MAX. Unit supply voltage supply voltage Normal operation Flash memory programming write supply current erase supply current Step erase time Overall erase time per area...
Page 714: Chapter 21 Package Drawing
CHAPTER 21 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 715: Chapter 22 Recommended Soldering Conditions
CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS User’s Manual U15109EJ3V0UD...
Page 716: Appendix Aregister Index
APPENDIX A REGISTER INDEX (1/11) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H (higher 8 bits) ADIC Interrupt control register ADM1 A/D converter mode register 1 ADM2 A/D converter mode register 2 Analog input channel specification register ASIM0 Asynchronous serial interface mode register 0 UART...
Page 717 APPENDIX A REGISTER INDEX (2/11) Symbol Name Unit Page C1IE CAN1 interrupt enable register FCAN C1INTP CAN1 interrupt pending register FCAN C1LAST CAN1 information register FCAN C1MASKH0 CAN1 address mask 0 register H FCAN C1MASKH1 CAN1 address mask 1 register H FCAN C1MASKH2 CAN1 address mask 2 register H...
Page 718 APPENDIX A REGISTER INDEX (3/11) Symbol Name Unit Page IEBus control data register IEBus CGCS CAN main clock select register FCAN CGIE CAN global interrupt enable register FCAN CGINTP CAN global interrupt pending register FCAN CGMSR CAN message search result register FCAN CGMSS CAN message search start register...
Page 719 APPENDIX A REGISTER INDEX (4/11) Symbol Name Unit Page CRC9 Capture/compare control register 9 CSIB4 Variable-length serial setting register 4 CSIC0 Interrupt control register INTC CSIC2 Interrupt control register INTC CSIC3 Interrupt control register INTC CSIC4 Interrupt control register INTC CSIC5 Interrupt control register INTC...
Page 720 APPENDIX A REGISTER INDEX (5/11) Symbol Name Unit Page IEBus telegraph length register IEBus DMAIC0 Interrupt control register INTC DMAIC1 Interrupt control register INTC DMAIC2 Interrupt control register INTC DMAIC3 Interrupt control register INTC DMAIC4 Interrupt control register INTC DMAIC5 Interrupt control register INTC DMAS...
Page 721 APPENDIX A REGISTER INDEX (6/11) Symbol Name Unit Page IEBus interrupt status register IEBus KRIC Interrupt control register INTC Key return mode register Memory address output mode register Port Memory expansion mode register Port M_CONF00 CAN message configuration registers 00 to 31 FCAN M_CONF31 M_CTRL00...
Page 722 APPENDIX A REGISTER INDEX (7/11) Symbol Name Unit Page Port 5 Port Port 6 Port Port 7 Port Port 8 Port Port 9 Port Port alternate-function control register Port PAC2 Port alternate-function control register 2 Port IEBus partner address register IEBus Processor clock control register Port 1 function register...
Page 723 APPENDIX A REGISTER INDEX (8/11) Symbol Name Unit Page PRM10 Prescaler mode register 10 PRM100 Prescaler mode register 100 PRM101 Prescaler mode register 101 PRM11 Prescaler mode register 11 PRM110 Prescaler mode register 110 PRM111 Prescaler mode register 111 PRM120 Prescaler mode register 120 PRM121 Prescaler mode register 121...
Page 724 APPENDIX A REGISTER INDEX (9/11) Symbol Name Unit Page SIRBEL6 Clocked serial interface read-only receive buffer register L6 SIRBL5 Clocked serial interface receive buffer register L5 SIRBL6 Clocked serial interface receive buffer register L6 SOTB5 Clocked serial interface transmit buffer register 5 SOTB6 Clocked serial interface transmit buffer register 6 SOTBF5...
Page 725 APPENDIX A REGISTER INDEX (10/11) Symbol Name Unit Page TMC11 16-bit timer mode control register 11 TMC12 16-bit timer mode control register 12 TMC50 Timer mode control register 50 TMC60 Timer mode control register 60 TMC7 16-bit timer mode control register 7 TMC8 16-bit timer mode control register 8 TMC9...
Page 726 APPENDIX A REGISTER INDEX (11/11) Symbol Name Unit Page VM45C VM45 control register Reset WDCS Watchdog timer clock select register WDTIC Interrupt control register INTC WDTM Watchdog timer mode register 238, 320 WTNCS Watch timer clock select register WTNHC Watch timer high-speed clock select register WTNIC Interrupt control register INTC...
Page 727: Appendix Blist Of Instruction Sets
APPENDIX B LIST OF INSTRUCTION SETS • How to read instruction set list This column shows instruction groups. Instructions are divided into each instruction group and described. This column shows instruction mnemonics. This column shows instruction operands (refer to Table B-1). This column shows instruction codes (op code) in binary format.
Page 728 APPENDIX B LIST OF INSTRUCTION SETS Table B-2. Symbols Used for Op Code Symbol Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data cccc 4-bit data that indicates condition code 3-bit data that specifies bit number...
Page 729 APPENDIX B LIST OF INSTRUCTION SETS Table B-4. Symbols Used for Flag Operation Symbol Description (blank) Not affected Cleared to 0 × Set of cleared according to result Previously saved value is restored Table B-5. Condition Codes Condition Name (cond) Condition Code (cccc) Conditional Expression Description...
Page 730 APPENDIX B LIST OF INSTRUCTION SETS Instruction Set List (1/4) Instruction Mnemonic Operand Op Code Operation Flag Group CY OV S Z SAT adr ← ep + zero-extend (disp7) Load/store SLD.B disp7 [ep], rrrrr0110ddddddd GR [reg2] ← sign-extend (Load-memory reg2 (adr, Byte)) adr ←...
Page 731 APPENDIX B LIST OF INSTRUCTION SETS Instruction Set List (2/4) Instruction Mnemonic Operand Op Code Operation Flag Group CY OV S Z SAT GR [reg2] ← GR [reg2] + GR [reg1] × × × × Arithmetic reg1, reg2 rrrrr001110RRRRR operation GR [reg2] ←...
Page 732 APPENDIX B LIST OF INSTRUCTION SETS Instruction Set List (3/4) Instruction Mnemonic Operand Op Code Operation Flag Group CY OV S Z SAT GR [reg2] ← GR [reg2] XOR GR [reg1] × × Logic reg1, reg2 rrrrr001001RRRRR operation GR [reg2] ← GR [reg1] XOR zero-extend ×...
Page 733 APPENDIX B LIST OF INSTRUCTION SETS Instruction Set List (4/4) Instruction Mnemonic Operand Op Code Operation Flag Group CY OV S Z SAT SR [regID] ←GR Special LDSR reg2, regID rrrrr111111RRRRR regID = EIPC, FEPC 0000000000100000 [reg2] regID = EIPSW, (Note) FEPSW ×...
Page 734: Appendix Crevision History
APPENDIX C REVISION HISTORY The following table shows the revision history up to the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/5) Edition Major Revision from Previous Edition Applied to: •...
Page 735 APPENDIX C REVISION HISTORY (2/5) Edition Major Revision from Previous Edition Applied to: Addition and modification of description in 8.1.3 (2) Capture/compare register n0 (CR00, CHAPTER 8 CR10, CR70 to CR120) TIMER/COUNTER FUNCTION Addition and modification of description in 8.1.3 (3) Capture/compare register n1 (CR01, CR11, CR71 to CR121) Addition to Cautions in 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12)
Page 736 APPENDIX C REVISION HISTORY (3/5) Edition Major Revision from Previous Edition Applied to: Addition to Cautions in Figure 11-47 BRGMCn0 and BRGMCn1 Settings CHAPTER 11 (Asynchronous Serial Interface Mode) SERIAL INTERFACE Addition of description in 11.6.3 (3) (d) Reception FUNCTION Deletion of description in 11.6.3 (3) (e) Receive error Modification of Note in Figure 11-52 Receive Error Timing Modification of Caution in 12.2 (2) A/D conversion result register (ADCR), A/D...
Page 737 APPENDIX C REVISION HISTORY (4/5) Edition Major Revision from Previous Edition Applied to: Modification of description on manipulatable bits and modification of bit description in CHAPTER 19 FCAN 19.5.14 CAN global interrupt enable register (CGIE) CONTROLLER (V850/SC3) Addition of description in 19.5.15 CAN main clock select register (CGCS) Deletion of Caution in Figure 19-2 FCAN Clocks Addition of Cautions and bit name, and modification of bit description in 19.5.17 CAN message search start/result register (CGMSS/CGMSR)
Page 738 APPENDIX C REVISION HISTORY (5/5) Edition Major Revision from Previous Edition Applied to: Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY User’s Manual U15109EJ3V0UD...
Page 739 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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Renesas v850/sc2 Renesas v850/sc3 Mpd703068y Mpd703069y Mpd703088y Mpd703089y ... Show all

NEC Renesas V850/SC1 User Manual

Chapter 1 Introduction

General

V850/Sc1

V850/Sc2

V850/Sc3

Chapter 2 Pin Functions

List of Pin Functions

Pin States

Description of Pin Functions

Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Functions

Features

CPU Register Set

Operating Modes

Address Space

Chapter 4 Clock Generation Function

General

Configuration

Clock Output Function

Power Save Functions

Oscillation Stabilization Time

Cautions on Power Save Function

Chapter 5 Port Functions

Port Configuration

Port Pin Functions

Setting When Port Pin Is Used for Alternate Function

Operation of Port Function

Chapter 6 Bus Control Function

Features

Bus Control Pins and Control Register

Bus Access

Memory Block Function

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Timing

Bus Priority

Memory Boundary Operation Condition

Chapter 7 Interrupt/Exception Processing Function

Outline

Non-Maskable Interrupts

Maskable Interrupts

Software Exceptions

Exception Trap

Priority Control

Response Time

Periods in Which Interrupts Are Not Acknowledged

Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer

Key Interrupt Function

Chapter 8 Timer/Counter Function

16-Bit Timer (TM0, TM1, TM7 to TM12)

16-Bit Timer (TM0, TM1, TM7 to TM12) Operation

16-Bit Timer (TM5, TM6)

16-Bit Timer (TM5, TM6) Operation

CHAPTER 10 Function

Chapter 9 Watch Timer Function

Configuration

Watch Timer Control Register

Operation

Watchdog Timer Function

Functions

Configuration

Watchdog Timer Control Registers

Operation

Standby Function Control Register

Chapter 11 Serial Interface Function

Overview

3-Wire Serial I/O (CSI0, CSI2, CSI3): 8 Bits

3-Wire Serial I/O (CSI4): 8 to 16 Bits Variable

3-Wire Serial I/O (CSI5, CSI6): 8 or 16 Bits

Asynchronous Serial Interface (UART0 to UART3)

Chapter 12 A/D Converter

Function

Configuration

Control Registers

Operation

Low-Power-Consumption Mode

Cautions