HP 13255 Technical Information page 31

13255
Cartrldge Tape Modul@
13255-91032/29
Rev AUG-Ol-7&
3.1.8 COMMAND RAMP AND FEEDBACK CIRCUITS - READ/WRITE PCA.
3.1.8
u
l The command ramp circuits translate command signals to move the tape
fast forward, slow forward, fast reverse, and slow reverse into ramped
voltages used by the CTU drive circuits. The feedbacK circuit provides
a VOltage directly proportional to the speed of the motor. The Feed-
baCK Voltage CrOSK VOLTAGE) and the Ramp Command Voltage (RAMP VOLTAGE)
are summed to provide an error signal for the power amplifiers in the
CTU drive circuits.
3.1.8
u
2 FPD, Sf 0, FREV and SREV run command lines drive open-collector TTL
inverters whiCh have 10 KilOhm pullup resistors to a 10-volt Zener
reference. unly one input should be pulled low at anyone time. These
commands cause the servo to drive at +60, +10, -60 and -10 ips. Fast
and slow command voltage values are determined
by
the relative values
of R12 through
RIS.
Reverse commands are inverted hefore being applied
to the ramp circuit by op-amp U6 (all op-amps are dual internally com-
pensated op-amp packages). The two op-amps (U8) make UP the ramp
circuit which together are analogous to a single inverting op-amp with
a slow linear slew rate. The first half of the ramp circuit is a high
gain (19&K divided by 1 kilOhm
=
196) voltage driver which supplies
bias current to a bidrectional voltage reference composed of CR5 and
CRb. This reference voltage (approximately
+1-6.9
volts) is supplied
to the second op-amp operated as a Miller integrator and has a slew
rate of 6.9 volts divided
by
R23, all divided by C21 (31 volts per
second). R22 feeds back the output of the integrator which sets the
dC gain of the ramp circuitry. The output for slow commands is +/-1.2
volts and for high speed commands is +/-7.2 volts.
Q3, Q4, U13, and op-amp Ub form a bidirectional threshold detector that
indicates the polarity of the command voltage as well as tne 1 ips
(either fOrward or reverse) threshold of the ramp command voltage,
generating the signals
+FDHK
EN and -FDBK EN.
3.1.8
u
3 The lACH FREQ and DELAYED TACH Signals go into an exclusive-OR qate
made up of U12 and two qates of U15. The output ot the exclusive-OR
gate is a pulse for every input transition, thus dOUbling the frequency
of the tach signal. This double frequency signal drives a precision
one-shot wnose output (93 microsecond period) is fed to one of two
TTL open·collector buffers
(UI0),
depending on the desired feedbaCK
polarity. The feedbaCK polarity is determined
by
the pOlarity of tne
command voltage. The +FDRK EN and -FDBK EN signals gate the one-shot
output to the appropriate TTL buffer. One TTL buffer output is In-
verted by the first half of U7, operated also as a 3 kHZ low pass