LG CED-8042B Manual page 21

System Controller Interface
Pin No. Pin Name
12~19 SA [15 :8]
20~27 SA [7 : 0]
29~32 SAD [7 : 0]
34~37
39 SALE
40 SRDY
41 SWEB/RWB
42 SREB/DSB
43 CS1B
44 CS0B
46 CPUTYPE
47, 48 SINT1,
SINT0
49 SRESB
44
Type
ADDRESS :
IN
Use these pins when access through 64Kbyte buffer memory window.
ADDRESS :
IN
Use these pins in case of connection with a microprocessor which has separated
address and data bus.
ADDRESS AND DATA : Address and data are multiplexed in a same pin.
I/O (PU)
In the case of input/output only data, fix SALE to GND.
These signals are Hi-Z when this LSI is reset.
ADDRESS LATCH ENABLE :
IN
Use this pin in case of connection with a microprocessor which has multiplexed
address and data bus.
READY : Data ready
OUT Selectable use/no use by setting internal registers.
(PU, TS)
In the case of access internal registers or buffer memory, this signal is asserted after
fixing driven data.
In case of no access, this pin is Hi-Z.
WRITE ENABLE/DATA READ WRITE STATUS : Write enable/data read write
status input for read.
IN
In the case of CPUTYPE = Open (: 86 type), this pin is write enable.
In the case of CPUTYPE = GND (: 68 type), this pin is read/write status.
READ ENABLE/DATA STROBE : Read enable /data strobe input for read
IN In the case of CPUTYPE = Open (: 86 type), this pin is read enable.
In the case of CPUTYPE = GND (: 68 type), this pin is data strobe.
IN CHIP SELECT 1 : Enable to access buffer memories.
IN CHIP SELECT 0 : Enable to access internal registers.
IN (PU) CPU TYPE SELECT : Microprocessor type select
Open : 86 type
GND : 68 type
SYSTEM INTERRUPT REQUEST 0,1 :
I/O (PU) Possible output pin whether SINT1 or SINT0 by using internal registers at each
interrupt groups (8bit unit)
SYSTEM RESET : Internal state machines are reset and all registers are set to default.
IN (PU) More than 1CLKIN active time is needed when assertion or negation of SRESB,
because it is through a de-glitch circuit.
Description